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Merge 2962f8fa88 into e436cc053f

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Martin Povišer 2024-11-29 10:13:51 +01:00 committed by GitHub
parent e436cc053f 2962f8fa88
commit 62e25a7ade
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1 changed files with 14 additions and 0 deletions
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14
passes/techmap/techmap.cc
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@ -1028,6 +1028,10 @@ struct TechmapPass : public Pass {
log(" map file. Note that the Verilog frontend is also called with the\n");
log(" '-nooverwrite' option set.\n");
log("\n");
log(" -dont_map <celltype>\n");
log(" ignore any mapping rules for the given cell type, that is leave it\n");
log(" unmapped.\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell. Multiple space-separated cell\n");
@ -1159,6 +1163,7 @@ struct TechmapPass : public Pass {
simplemap_get_mappers(worker.simplemap_mappers);
std::vector<std::string> map_files;
std::vector<RTLIL::IdString> dont_map;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
int max_iter = -1;
@ -1200,6 +1205,10 @@ struct TechmapPass : public Pass {
worker.ignore_wb = true;
continue;
}
if (args[argidx] == "-dont_map" && argidx+1 < args.size()) {
dont_map.push_back(RTLIL::escape_id(args[++argidx]));
continue;
}
break;
}
extra_args(args, argidx, design);
@ -1256,6 +1265,11 @@ struct TechmapPass : public Pass {
celltypeMap[module_name].insert(module->name);
}
}
// Erase any rules disabled with a -dont_map argument
for (auto type : dont_map)
celltypeMap.erase(type);
log_debug("Cell type mappings to use:\n");
for (auto &i : celltypeMap) {
i.second.sort(RTLIL::sort_by_id_str());