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Map to and from this box if -abc9

This commit is contained in:
Eddie Hung 2019-07-12 00:53:01 -07:00
parent 0f5bddcd79
commit 62ac5ebd02
1 changed files with 3 additions and 2 deletions
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5
techlibs/ice40/synth_ice40.cc
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@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass
{ {
if (check_label("begin")) if (check_label("begin"))
{ {
run("read_verilog -lib -D_ABC +/ice40/cells_sim.v"); run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc"); run("proc");
} }
@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
if (nocarry) if (nocarry)
run("techmap"); run("techmap");
else else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
if (retime || help_mode) if (retime || help_mode)
run(abc + " -dff", "(only if -retime)"); run(abc + " -dff", "(only if -retime)");
run("ice40_opt"); run("ice40_opt");
@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass
else else
wire_delay = 250; wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
} }
else else
run(abc + " -dress -lut 4", "(skip if -noabc)"); run(abc + " -dress -lut 4", "(skip if -noabc)");