diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc
index 1098bc8f6..bed1ba572 100644
--- a/techlibs/quicklogic/ql_bram_merge.cc
+++ b/techlibs/quicklogic/ql_bram_merge.cc
@@ -31,9 +31,6 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct QlBramMergeWorker {
 
-	const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
-	const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
-
 	// can be used to record parameter values that have to match on both sides
 	typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
 
@@ -42,6 +39,8 @@ struct QlBramMergeWorker {
 
 	QlBramMergeWorker(RTLIL::Module* module) : module(module)
 	{
+		const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
+
 		for (RTLIL::Cell* cell : module->selected_cells())
 		{
 			if(cell->type != split_cell_type) continue;
@@ -125,6 +124,7 @@ struct QlBramMergeWorker {
 
 	void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
 	{
+		const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
 
 		// Create the new cell
 		RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc
index 523c86e73..ecf163dbf 100644
--- a/techlibs/quicklogic/ql_dsp_io_regs.cc
+++ b/techlibs/quicklogic/ql_dsp_io_regs.cc
@@ -30,10 +30,6 @@ PRIVATE_NAMESPACE_BEGIN
 // ============================================================================
 
 struct QlDspIORegs : public Pass {
-	const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
-													 ID(saturate_enable), ID(shift_right), ID(round)};
-	const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
-
 	SigMap sigmap;
 
 	// ..........................................
@@ -67,6 +63,11 @@ struct QlDspIORegs : public Pass {
 
 	void ql_dsp_io_regs_pass(RTLIL::Module *module)
 	{
+		static const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
+														ID(saturate_enable), ID(shift_right), ID(round)};
+		static const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
+
+
 		sigmap.set(module);
 
 		for (auto cell : module->cells()) {
diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc
index 153f3995f..9df979c33 100644
--- a/techlibs/quicklogic/ql_dsp_simd.cc
+++ b/techlibs/quicklogic/ql_dsp_simd.cc
@@ -60,43 +60,11 @@ struct QlDspSimdPass : public Pass {
 
 	// ..........................................
 
-	// DSP control and config ports to consider and how to map them to ports
-	// of the target DSP cell
-	const std::vector<std::pair<IdString, IdString>> m_DspCfgPorts = {
-		std::make_pair(ID(clock_i), ID(clk)),
-		std::make_pair(ID(reset_i), ID(reset)),
-		std::make_pair(ID(feedback_i), ID(feedback)),
-		std::make_pair(ID(load_acc_i), ID(load_acc)),
-		std::make_pair(ID(unsigned_a_i), ID(unsigned_a)),
-		std::make_pair(ID(unsigned_b_i), ID(unsigned_b)),
-		std::make_pair(ID(subtract_i), ID(subtract)),
-		std::make_pair(ID(output_select_i), ID(output_select)),
-		std::make_pair(ID(saturate_enable_i), ID(saturate_enable)),
-		std::make_pair(ID(shift_right_i), ID(shift_right)),
-		std::make_pair(ID(round_i), ID(round)),
-		std::make_pair(ID(register_inputs_i), ID(register_inputs))
-	};
-
 	const int m_ModeBitsSize = 80;
 
-	// DSP data ports and how to map them to ports of the target DSP cell
-	const std::vector<std::pair<IdString, IdString>> m_DspDataPorts = {
-		std::make_pair(ID(a_i), ID(a)),
-		std::make_pair(ID(b_i), ID(b)),
-		std::make_pair(ID(acc_fir_i), ID(acc_fir)),
-		std::make_pair(ID(z_o), ID(z)),
-		std::make_pair(ID(dly_b_o), ID(dly_b))
-	};
-
 	// DSP parameters
 	const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
 
-	// Source DSP cell type (SISD)
-	const IdString m_SisdDspType = ID(dsp_t1_10x9x32);
-
-	// Target DSP cell types for the SIMD mode
-	const IdString m_SimdDspType = ID(QL_DSP2);
-
 	/// Temporary SigBit to SigBit helper map.
 	SigMap sigmap;
 
@@ -106,6 +74,38 @@ struct QlDspSimdPass : public Pass {
 	{
 		log_header(a_Design, "Executing QL_DSP_SIMD pass.\n");
 
+		// DSP control and config ports to consider and how to map them to ports
+		// of the target DSP cell
+		static const std::vector<std::pair<IdString, IdString>> m_DspCfgPorts = {
+			std::make_pair(ID(clock_i), ID(clk)),
+			std::make_pair(ID(reset_i), ID(reset)),
+			std::make_pair(ID(feedback_i), ID(feedback)),
+			std::make_pair(ID(load_acc_i), ID(load_acc)),
+			std::make_pair(ID(unsigned_a_i), ID(unsigned_a)),
+			std::make_pair(ID(unsigned_b_i), ID(unsigned_b)),
+			std::make_pair(ID(subtract_i), ID(subtract)),
+			std::make_pair(ID(output_select_i), ID(output_select)),
+			std::make_pair(ID(saturate_enable_i), ID(saturate_enable)),
+			std::make_pair(ID(shift_right_i), ID(shift_right)),
+			std::make_pair(ID(round_i), ID(round)),
+			std::make_pair(ID(register_inputs_i), ID(register_inputs))
+		};
+
+		// DSP data ports and how to map them to ports of the target DSP cell
+		static const std::vector<std::pair<IdString, IdString>> m_DspDataPorts = {
+			std::make_pair(ID(a_i), ID(a)),
+			std::make_pair(ID(b_i), ID(b)),
+			std::make_pair(ID(acc_fir_i), ID(acc_fir)),
+			std::make_pair(ID(z_o), ID(z)),
+			std::make_pair(ID(dly_b_o), ID(dly_b))
+		};
+
+		// Source DSP cell type (SISD)
+		static const IdString m_SisdDspType = ID(dsp_t1_10x9x32);
+
+		// Target DSP cell types for the SIMD mode
+		static const IdString m_SimdDspType = ID(QL_DSP2);
+
 		// Parse args
 		extra_args(a_Args, 1, a_Design);
 
@@ -126,7 +126,7 @@ struct QlDspSimdPass : public Pass {
 					continue;
 
 				// Add to a group
-				const auto key = getDspConfig(cell);
+				const auto key = getDspConfig(cell, m_DspCfgPorts);
 				groups[key].push_back(cell);
 			}
 
@@ -255,11 +255,11 @@ struct QlDspSimdPass : public Pass {
 	}
 
 	/// Given a DSP cell populates and returns a DspConfig struct for it.
-	DspConfig getDspConfig(RTLIL::Cell *a_Cell)
+	DspConfig getDspConfig(RTLIL::Cell *a_Cell, const std::vector<std::pair<IdString, IdString>> &dspCfgPorts)
 	{
 		DspConfig config;
 
-		for (const auto &it : m_DspCfgPorts) {
+		for (const auto &it : dspCfgPorts) {
 			auto port = it.first;
 
 			// Port unconnected