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Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_const 

Add optimization to rtlil back-end for all-x parameter values
This commit is contained in:
Miodrag Milanović 2021-09-28 18:03:14 +02:00 committed by GitHub
parent 7a7df9a3b4 89df26e4bc
commit 62739f7bf7
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 9 deletions
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22
backends/rtlil/rtlil_backend.cc
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@ -51,15 +51,19 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
}
}
f << stringf("%d'", width);
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("-"); break;
case RTLIL::Sm: f << stringf("m"); break;
if (data.is_fully_undef()) {
f << "x";
} else {
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("-"); break;
case RTLIL::Sm: f << stringf("m"); break;
}
}
}
} else {