mirror of https://github.com/YosysHQ/yosys.git
booth: Remove more of unused helpers
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30f8387b75
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@ -66,47 +66,6 @@ struct BoothPassWorker {
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BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; }
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BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; }
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// Unary gate
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RTLIL::Wire *mk_ugate1(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, std::string &op_name)
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{
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std::string op_wire_name;
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if (op_name.empty())
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op_wire_name = name + "_o";
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else
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op_wire_name = op_name;
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RTLIL::Wire *ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1);
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auto g = module->addCell(new_id(name, __LINE__, ""), red_typ);
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g->setPort(ID::A, ip1);
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g->setPort(ID::Y, ret);
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g->setParam(ID::A_SIGNED, false);
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g->setParam(ID::A_WIDTH, 1);
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g->setParam(ID::Y_WIDTH, 1);
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return ret;
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}
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// Binary gate
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RTLIL::Wire *mk_ugate2(const RTLIL::IdString &red_typ, std::string &name, SigBit ip1, SigBit ip2, std::string &op_name)
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{
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auto g = module->addCell(new_id(name, __LINE__, ""), red_typ);
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std::string op_wire_name;
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if (op_name.empty())
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op_wire_name = name + "_o";
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else
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op_wire_name = op_name;
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auto ret = module->addWire(new_id(op_wire_name, __LINE__, ""), 1);
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g->setPort(ID::A, ip1);
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g->setPort(ID::B, ip2);
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g->setPort(ID::Y, ret);
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g->setParam(ID::A_SIGNED, false);
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g->setParam(ID::B_SIGNED, false);
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g->setParam(ID::A_WIDTH, 1);
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g->setParam(ID::B_WIDTH, 1);
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g->setParam(ID::Y_WIDTH, 1);
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return ret;
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}
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// Booth unsigned decoder lsb
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// Booth unsigned decoder lsb
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SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
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SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
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{
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{
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