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Updated TODOs

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Clifford Wolf 2013-11-24 17:58:05 +01:00
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commit 620b7c900a
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@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs
- yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
- Technology mapping for real-world applications - Technology mapping for real-world applications
- Add "mini synth script" feature to techmap pass - Add bit-wise const-folding via cell parameters to techmap pass
- Add const-folding via cell parameters to techmap pass
- Rewrite current stdcells.v techmap rules (modular and clean) - Rewrite current stdcells.v techmap rules (modular and clean)
- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)