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Merge pull request #1633 from YosysHQ/eddie/fix_autoname 

autoname: do not rename ports
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Eddie Hung 2020-01-14 11:40:54 -08:00 committed by GitHub
parent 9fa0e03cc9 de969adcd8
commit 61ffd2d199
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2 changed files with 20 additions and 1 deletions
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2
passes/cmds/autoname.cc
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@ -56,7 +56,7 @@ int autoname_worker(Module *module)
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
string suffix = stringf("_%s", log_id(conn.first)); string suffix = stringf("_%s", log_id(conn.first));
for (auto bit : conn.second) for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] == '$') { if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
IdString new_name(cell->name.str() + suffix); IdString new_name(cell->name.str() + suffix);
int score = wire_score.at(bit.wire); int score = wire_score.at(bit.wire);
if (cell->output(conn.first)) score = 0; if (cell->output(conn.first)) score = 0;

19
tests/various/autoname.ys Normal file
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@ -0,0 +1,19 @@
read_ilang <<EOT
autoidx 2
module \top
wire output 3 $y
wire input 1 \a
wire input 2 \b
cell $and \b_$and_B
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
connect \Y $y
end
end
EOT
autoname