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Update tests

This commit is contained in:
Miodrag Milanovic 2023-03-18 18:12:02 +01:00 committed by myrtle
parent ff9f1fb86e
commit 61da330a38
7 changed files with 16 additions and 16 deletions
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2
tests/arch/machxo2/add_sub.ys
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@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4 select -assert-count 10 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

8
tests/arch/machxo2/dffs.ys
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@ -6,8 +6,8 @@ proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FACADE_FF select -assert-count 1 t:TRELLIS_FF
select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
@ -15,5 +15,5 @@ proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:FACADE_FF t:LUT4 select -assert-count 2 t:TRELLIS_FF t:LUT4
select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D

4
tests/arch/machxo2/fsm.ys
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@ -11,5 +11,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd fsm # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
select -assert-max 16 t:LUT4 select -assert-max 16 t:LUT4
select -assert-count 6 t:FACADE_FF select -assert-count 6 t:TRELLIS_FF
select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D

2
tests/arch/machxo2/logic.ys
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@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4 select -assert-count 9 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

8
tests/arch/machxo2/mux.ys
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@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux4 hierarchy -top mux4
@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux8 hierarchy -top mux8
@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4 select -assert-count 5 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux16 hierarchy -top mux16
@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4 select -assert-max 12 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

4
tests/arch/machxo2/shifter.ys
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@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:FACADE_FF select -assert-count 8 t:TRELLIS_FF
select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D

4
tests/arch/machxo2/tribuf.ys
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@ -5,6 +5,6 @@ flatten
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module cd tristate # Constrain all select calls below inside the top module
select -assert-count 3 t:FACADE_IO select -assert-count 3 t:TRELLIS_IO
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
select -assert-none t:FACADE_IO t:LUT4 %% t:* %D select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D