Merge pull request #4789 from YosysHQ/emil/sklansky-adder

Add a Sklansky option for `$lcu` mapping
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Emil J 2024-12-03 11:33:13 +01:00 committed by GitHub
commit 61a6567b9f
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3 changed files with 53 additions and 0 deletions

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@ -37,3 +37,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v)) $(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v)) $(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/sklansky.v))

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@ -0,0 +1,37 @@
(* techmap_celltype = "$lcu" *)
module _80_lcu_sklansky (P, G, CI, CO);
parameter WIDTH = 2;
(* force_downto *)
input [WIDTH-1:0] P, G;
input CI;
(* force_downto *)
output [WIDTH-1:0] CO;
integer i, j;
(* force_downto *)
reg [WIDTH-1:0] p, g;
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
always @* begin
p = P;
g = G;
// in almost all cases CI will be constant zero
g[0] = g[0] | (p[0] & CI);
for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
// iterate in reverse so we don't confuse a result from this stage and the previous
for (j = WIDTH - 1; j >= 0; j = j - 1) begin
if (j & 2**i) begin
g[j] = g[j] | p[j] & g[(j & ~(2**i - 1)) - 1];
p[j] = p[j] & p[(j & ~(2**i - 1)) - 1];
end
end
end
end
assign CO = g;
endmodule

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@ -0,0 +1,15 @@
yosys -import
read_verilog +/choices/sklansky.v
read_verilog -icells lcu_refined.v
design -save init
for {set i 1} {$i <= 16} {incr i} {
design -load init
chparam -set WIDTH $i
yosys proc
opt_clean
equiv_make lcu _80_lcu_sklansky equiv
equiv_simple equiv
equiv_status -assert equiv
}