From 684c85902d259a0db3ac5271b540549e98646306 Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 26 May 2014 17:13:41 +0200 Subject: [PATCH 1/3] be more verbose when techmap yielded processes --- passes/techmap/techmap.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 69ffb9230..4c5a0febc 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -106,8 +106,12 @@ struct TechmapWorker if (tpl->memories.size() != 0) log_error("Technology map yielded memories -> this is not supported.\n"); - if (tpl->processes.size() != 0) + if (tpl->processes.size() != 0) { + log("Technology map yielded processes:\n"); + for (auto &it : tpl->processes) + log(" %s",RTLIL::id2cstr(it.first)); log_error("Technology map yielded processes -> this is not supported.\n"); + } // erase from namespace first for _TECHMAP_REPLACE_ to work module->cells.erase(cell->name); From 63dfbb18cfb34d72746565a3eb3ffbcd7451cdab Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Wed, 28 May 2014 16:50:13 +0200 Subject: [PATCH 2/3] new flags -ignore_miss_func and -ignore_miss_dir for read_liberty --- frontends/liberty/liberty.cc | 44 ++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 485d28ee1..285491e06 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -459,6 +459,13 @@ struct LibertyFrontend : public Frontend { log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" create an error message.)\n"); log("\n"); + log(" -ignore_miss_func\n"); + log(" ignore cells with missing function specification of outputs\n"); + log("\n"); + log(" -ignore_miss_dir\n"); + log(" ignore cells with a missing or invalid direction\n"); + log(" specification on a pin\n"); + log("\n"); log(" -setattr \n"); log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); @@ -467,6 +474,8 @@ struct LibertyFrontend : public Frontend { { bool flag_lib = false; bool flag_ignore_redef = false; + bool flag_ignore_miss_func = false; + bool flag_ignore_miss_dir = false; std::vector attributes; log_header("Executing Liberty frontend.\n"); @@ -482,6 +491,14 @@ struct LibertyFrontend : public Frontend { flag_ignore_redef = true; continue; } + if (arg == "-ignore_miss_func") { + flag_ignore_miss_func = true; + continue; + } + if (arg == "-ignore_miss_dir") { + flag_ignore_miss_dir = true; + continue; + } if (arg == "-setattr" && argidx+1 < args.size()) { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; @@ -507,11 +524,9 @@ struct LibertyFrontend : public Frontend { } // log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name)); - cell_count++; RTLIL::Module *module = new RTLIL::Module; module->name = cell_name; - design->modules[module->name] = module; for (auto &attr : attributes) module->attributes[attr] = 1; @@ -520,7 +535,16 @@ struct LibertyFrontend : public Frontend { if (node->id == "pin" && node->args.size() == 1) { LibertyAst *dir = node->find("direction"); if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "internal")) - log_error("Missing or invalid dircetion for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name)); + { + if (!flag_ignore_miss_dir) + { + log_error("Missing or invalid dircetion for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name)); + } else { + log("Ignoring cell %s with missing or invalid dircetion for pin %s.\n", RTLIL::id2cstr(module->name), node->args.at(0).c_str()); + delete module; + goto skip_cell; + } + } if (!flag_lib || dir->value != "internal") module->new_wire(1, RTLIL::escape_id(node->args.at(0))); } @@ -556,7 +580,16 @@ struct LibertyFrontend : public Frontend { LibertyAst *func = node->find("function"); if (func == NULL) - log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name)); + { + if (!flag_ignore_miss_func) + { + log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name)); + } else { + log("Ignoring cell %s with missing function on output %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + delete module; + goto skip_cell; + } + } RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str()); module->connections.push_back(RTLIL::SigSig(wire, out_sig)); @@ -564,6 +597,9 @@ struct LibertyFrontend : public Frontend { } module->fixup_ports(); + design->modules[module->name] = module; + cell_count++; +skip_cell:; } log("Imported %d cell types from liberty file.\n", cell_count); From 278085fa01a9013051fbec842314cb6b5642e9bb Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Wed, 28 May 2014 18:05:38 +0200 Subject: [PATCH 3/3] added log_header to miter and expose pass, show cell type for exposed ports --- passes/sat/expose.cc | 8 +++++--- passes/sat/miter.cc | 4 ++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 2ac7b35f6..831a43aa5 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -259,6 +259,8 @@ struct ExposePass : public Pass { bool flag_evert_dff = false; std::string sep = "."; + log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n"); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -629,7 +631,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; if (cell->connections.count(p->name) != 0) @@ -654,7 +656,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) module->connections.push_back(RTLIL::SigSig(it.second, w)); @@ -667,7 +669,7 @@ struct ExposePass : public Pass { } for (auto &it : delete_cells) { - log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it)); + log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type)); delete module->cells.at(it); module->cells.erase(it); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index db12cb57d..6c8e2ff48 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, bool flag_make_outcmp = false; bool flag_make_assert = false; + log_header("Executing MITER pass (creating miter circuit).\n"); + size_t argidx; for (argidx = 2; argidx < args.size(); argidx++) { @@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str()); } + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); + RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; design->modules[miter_name] = miter_module;