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Resolve package types in interfaces (#3658) 

* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
This commit is contained in:
Dag Lem 2023-02-13 00:25:39 +01:00 committed by GitHub
parent 5ea2c290a5
commit 615adc4253
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 34 additions and 3 deletions
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6
frontends/ast/simplify.cc
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@ -1016,7 +1016,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// create name resolution entries for all objects with names
// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
if (type == AST_MODULE) {
if (type == AST_MODULE || type == AST_INTERFACE) {
current_scope.clear();
std::set<std::string> existing;
int counter = 0;
@ -1701,7 +1701,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
current_filename = filename;
if (type == AST_MODULE)
if (type == AST_MODULE || type == AST_INTERFACE)
current_scope.clear();
// convert defparam nodes to cell parameters
@ -4691,7 +4691,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
children_flags |= AstNode::MEM2REG_FL_ALL;
dict<AstNode*, uint32_t> *proc_flags_p = NULL;

24
tests/svinterfaces/resolve_types.sv Normal file
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@ -0,0 +1,24 @@
// This test checks that types, including package types, are resolved from within an interface.
typedef logic [7:0] x_t;
package pkg;
typedef logic [7:0] y_t;
endpackage
interface iface;
x_t x;
pkg::y_t y;
endinterface
module dut (input logic [7:0] x, output logic [7:0] y);
iface intf();
assign intf.x = x;
assign y = intf.y;
ondemand u(.intf);
endmodule
module ref (input logic [7:0] x, output logic [7:0] y);
assign y = ~x;
endmodule

6
tests/svinterfaces/resolve_types.ys Normal file
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@ -0,0 +1,6 @@
read_verilog -sv resolve_types.sv
hierarchy -libdir . -check
flatten
equiv_make ref dut equiv
equiv_simple
equiv_status -assert

1
tests/svinterfaces/run-test.sh
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@ -4,3 +4,4 @@
./runone.sh svinterface_at_top
./run_simple.sh load_and_derive
./run_simple.sh resolve_types