mirror of https://github.com/YosysHQ/yosys.git
Fix input/output attributes when resolving typedef of wire
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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parent
09071afe15
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61501e3266
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@ -1330,6 +1330,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {
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if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {
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// replace with wire representing the packed structure
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// replace with wire representing the packed structure
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newNode = make_packed_struct(template_node, str);
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newNode = make_packed_struct(template_node, str);
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// add original input/output attribute to resolved wire
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newNode->is_input = this->is_input;
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newNode->is_output = this->is_output;
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current_scope[str] = this;
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current_scope[str] = this;
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goto apply_newNode;
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goto apply_newNode;
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}
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}
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