mirror of https://github.com/YosysHQ/yosys.git
hotfix for ModInfo
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@ -70,7 +70,7 @@ struct ModIndex : public RTLIL::Monitor
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SigMap sigmap;
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RTLIL::Module *module;
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dict<RTLIL::SigBit, SigBitInfo> database;
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std::map<RTLIL::SigBit, SigBitInfo> database;
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bool auto_reload_module;
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void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
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