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Transpose CARRY4 delays

This commit is contained in:
Eddie Hung 2019-05-24 14:09:15 -07:00
parent 52e9036d39
commit 60af2ca94d
1 changed files with 8 additions and 10 deletions
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18
techlibs/xilinx/abc.box
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@ -15,16 +15,14 @@ MUXF8 2 1 3 1
# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
CARRY4 3 1 10 8 CARRY4 3 1 10 8
271 157 228 114 222 334 239 313 271 536 379 - - - 340 - - -
536 494 592 580 482 598 584 642 157 494 465 445 - - 433 469 - -
379 465 540 526 - 407 556 615 228 592 540 520 356 - 512 548 292 -
- 445 520 507 - - 537 596 114 580 526 507 398 385 508 528 378 380
- - 356 398 - - - 438 222 482 - - - - 223 - - -
- - - 385 - - - - 334 598 407 - - - 400 205 - -
340 433 512 508 223 400 523 582 239 584 556 537 - - 523 558 226 -
- 469 548 528 - 205 558 618 313 642 615 596 438 - 582 618 330 227
- - 292 376 - - 226 330
- - - 380 - - - 227
# SLICEM/A6LUT # SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE