From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Wed, 15 Aug 2018 19:56:30 +0300 Subject: [PATCH 1/7] A few minor enhancements to specify block parsing. Just remember specify blocks are parsed but ignored. --- frontends/verilog/verilog_parser.y | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 78cac5543..61da12b76 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -688,8 +688,8 @@ path_declaration : ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' - // | full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value ';' | + full_path_description '=' path_delay_value ';' ; path_delay_value : @@ -723,6 +723,17 @@ list_of_path_delay_expressions : parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; +full_path_description : + '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + +list_of_path_inputs : + specify_input_terminal_descriptor | + list_of_path_inputs ',' specify_input_terminal_descriptor ; + +list_of_path_outputs : + specify_output_terminal_descriptor | + list_of_path_outputs ',' specify_output_terminal_descriptor ; + opt_polarity_operator : '+' | '-' From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 00:08:08 +0300 Subject: [PATCH 2/7] Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value. --- frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 61da12b76..58a6824d1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -654,7 +654,7 @@ specify_item: // | pulsestyle_declaration // | showcancelled_declaration | path_declaration - // | system_timing_declaration + | system_timing_declaration ; specparam_declaration: @@ -693,8 +693,8 @@ simple_path_declaration : ; path_delay_value : - //list_of_path_delay_expressions - '(' list_of_path_delay_expressions ')' + list_of_path_delay_expressions | + %prec '(' list_of_path_delay_expressions ')' ; list_of_path_delay_expressions : @@ -724,12 +724,17 @@ parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; full_path_description : - '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ; +// This was broken into 2 rules to solve shift/reduce conflicts list_of_path_inputs : - specify_input_terminal_descriptor | - list_of_path_inputs ',' specify_input_terminal_descriptor ; - + specify_input_terminal_descriptor opt_polarity_operator | + specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ; + +more_path_inputs : + ',' specify_input_terminal_descriptor | + more_path_inputs ',' specify_input_terminal_descriptor ; + list_of_path_outputs : specify_output_terminal_descriptor | list_of_path_outputs ',' specify_output_terminal_descriptor ; @@ -747,11 +752,18 @@ specify_input_terminal_descriptor : specify_output_terminal_descriptor : TOK_ID ; -/* system_timing_declaration : - ; -*/ + TOK_ID '(' system_timing_args ')' ';' ; +system_timing_arg : + TOK_POSEDGE TOK_ID | + TOK_NEGEDGE TOK_ID | + expr ; + +system_timing_args : + system_timing_arg | + system_timing_args ',' system_timing_arg ; + /* t_path_delay_expression : path_delay_expression; From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 17:27:45 +0300 Subject: [PATCH 3/7] Fixed all known specify/endspecify issues, without breaking 'make test'. Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses --- frontends/verilog/verilog_parser.y | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 58a6824d1..2389d7d31 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -682,22 +682,23 @@ showcancelled_declaration : */ path_declaration : - simple_path_declaration + simple_path_declaration ';' // | edge_sensitive_path_declaration // | state_dependent_path_declaration ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' | - full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value | + full_path_description '=' path_delay_value ; path_delay_value : - list_of_path_delay_expressions | - %prec '(' list_of_path_delay_expressions ')' + '(' path_delay_expression list_of_path_delay_extra_expressions ')' + | path_delay_expression + | path_delay_expression list_of_path_delay_extra_expressions ; -list_of_path_delay_expressions : +list_of_path_delay_extra_expressions : /* t_path_delay_expression | trise_path_delay_expression ',' tfall_path_delay_expression @@ -709,12 +710,11 @@ list_of_path_delay_expressions : t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression */ - path_delay_expression - | path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression @@ -815,7 +815,7 @@ tzx_path_delay_expression : */ path_delay_expression : - constant_mintypmax_expression; + constant_expression; constant_mintypmax_expression : constant_expression From 042b3074f8096212b3f2114d353b2ec75818810b Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Thu, 23 Aug 2018 15:19:46 +0300 Subject: [PATCH 4/7] Added -no_dump_ptr flag for AST dump options in 'read_verilog' This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. --- frontends/ast/ast.cc | 15 +++++++++------ frontends/ast/ast.h | 4 ++-- frontends/verilog/verilog_frontend.cc | 10 +++++++++- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7c72a50d9..e79be953a 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -44,7 +44,7 @@ namespace AST { // instanciate global variables (private API) namespace AST_INTERNAL { - bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; @@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const std::string type_name = type2str(type); fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum); - if (id2ast) - fprintf(f, " [%p -> %p]", this, id2ast); - else - fprintf(f, " [%p]", this); + if (!flag_no_dump_ptr) { + if (id2ast) + fprintf(f, " [%p -> %p]", this, id2ast); + else + fprintf(f, " [%p]", this); + } if (!str.empty()) fprintf(f, " str='%s'", str.c_str()); @@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer) } // create AstModule instances for all modules in the AST tree and add them to 'design' -void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, +void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; flag_dump_ast2 = dump_ast2; + flag_no_dump_ptr = no_dump_ptr; flag_dump_vlog = dump_vlog; flag_dump_rtlil = dump_rtlil; flag_nolatches = nolatches; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d94199643..7e97bdb3b 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -274,7 +274,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library @@ -305,7 +305,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 911e36112..8dcc7c5aa 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend { log(" -dump_ast2\n"); log(" dump abstract syntax tree (after simplification)\n"); log("\n"); + log(" -no_dump_ptr\n"); + log(" do not include hex memory addresses in dump (easier to diff dumps)\n"); + log("\n"); log(" -dump_vlog\n"); log(" dump ast as Verilog code (after simplification)\n"); log("\n"); @@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend { { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; + bool flag_no_dump_ptr = false; bool flag_dump_vlog = false; bool flag_dump_rtlil = false; bool flag_nolatches = false; @@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend { flag_dump_ast2 = true; continue; } + if (arg == "-no_dump_ptr") { + flag_no_dump_ptr = true; + continue; + } if (arg == "-dump_vlog") { flag_dump_vlog = true; continue; @@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; From 306a010e199d9318472c9c08eb16117bd83c7257 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 25 Aug 2018 16:20:44 +0200 Subject: [PATCH 5/7] static link flag on main executable --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c1e5c789d..18bf303b1 100644 --- a/Makefile +++ b/Makefile @@ -158,7 +158,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),gcc-static) LD = $(CXX) -LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s +LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static LDLIBS := $(filter-out -lrt,$(LDLIBS)) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) CXXFLAGS += -std=c++11 -Os From 9e845bd25460d7b8287cf3ea5147040689940f49 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Aug 2018 13:27:05 +0200 Subject: [PATCH 6/7] Add ENABLE_GCOV build option Signed-off-by: Clifford Wolf --- Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile b/Makefile index 18bf303b1..7eb3971f7 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 # other configuration flags +ENABLE_GCOV := 0 ENABLE_GPROF := 0 ENABLE_DEBUG := 0 ENABLE_NDEBUG := 0 @@ -312,6 +313,11 @@ endif endif endif +ifeq ($(ENABLE_GCOV),1) +CXXFLAGS += --coverage +LDFLAGS += --coverage +endif + ifeq ($(ENABLE_GPROF),1) CXXFLAGS += -pg LDFLAGS += -pg @@ -709,6 +715,11 @@ config-msys2: clean config-msys2-64: clean echo 'CONFIG := msys2-64' > Makefile.conf +config-gcov: clean + echo 'CONFIG := gcc' > Makefile.conf + echo 'ENABLE_GCOV := 1' >> Makefile.conf + echo 'ENABLE_DEBUG := 1' >> Makefile.conf + config-gprof: clean echo 'CONFIG := gcc' > Makefile.conf echo 'ENABLE_GPROF := 1' >> Makefile.conf From ddc1761f1a443ea9560c67cfc126160ba7254a39 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Aug 2018 14:22:21 +0200 Subject: [PATCH 7/7] Add "make coverage" Signed-off-by: Clifford Wolf --- .gitignore | 4 ++++ Makefile | 8 +++++++- frontends/ilang/.gitignore | 2 +- frontends/ilang/Makefile.inc | 7 +++---- frontends/ilang/ilang_lexer.l | 2 +- frontends/verilog/.gitignore | 2 +- frontends/verilog/Makefile.inc | 7 +++---- frontends/verilog/verilog_lexer.l | 2 +- 8 files changed, 21 insertions(+), 13 deletions(-) diff --git a/.gitignore b/.gitignore index cd624f233..4fce690ec 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,8 @@ *.d .*.swp *.gch +*.gcda +*.gcno /.cproject /.project /.settings @@ -10,6 +12,8 @@ /qtcreator.config /qtcreator.creator /qtcreator.creator.user +/coverage.info +/coverage_html /Makefile.conf /abc /viz.js diff --git a/Makefile b/Makefile index 7eb3971f7..39a361a5f 100644 --- a/Makefile +++ b/Makefile @@ -650,6 +650,12 @@ clean-abc: mrproper: clean git clean -xdf +coverage: + ./yosys -qp 'help; help -all' + rm -rf coverage.info coverage_html + lcov --capture -d . --no-external -o coverage.info + genhtml coverage.info --output-directory coverage_html + qtcreator: { for file in $(basename $(OBJS)); do \ for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \ @@ -740,6 +746,6 @@ echo-git-rev: -include kernel/*.d -include techlibs/*/*.d -.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator +.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore index 43106a814..f586b33c7 100644 --- a/frontends/ilang/.gitignore +++ b/frontends/ilang/.gitignore @@ -1,4 +1,4 @@ ilang_lexer.cc ilang_parser.output ilang_parser.tab.cc -ilang_parser.tab.h +ilang_parser.tab.hh diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc index e2a476c93..6f1f0e8fc 100644 --- a/frontends/ilang/Makefile.inc +++ b/frontends/ilang/Makefile.inc @@ -1,15 +1,14 @@ GENFILES += frontends/ilang/ilang_parser.tab.cc -GENFILES += frontends/ilang/ilang_parser.tab.h +GENFILES += frontends/ilang/ilang_parser.tab.hh GENFILES += frontends/ilang/ilang_parser.output GENFILES += frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $< - $(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc + $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $< -frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc +frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l $(Q) mkdir -p $(dir $@) diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index 842388548..d8e01ae4d 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -30,7 +30,7 @@ #endif #include "frontends/ilang/ilang_frontend.h" -#include "ilang_parser.tab.h" +#include "ilang_parser.tab.hh" USING_YOSYS_NAMESPACE diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore index 1d4ae9e5c..aadbcdcdd 100644 --- a/frontends/verilog/.gitignore +++ b/frontends/verilog/.gitignore @@ -1,4 +1,4 @@ verilog_lexer.cc verilog_parser.output verilog_parser.tab.cc -verilog_parser.tab.h +verilog_parser.tab.hh diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index a06c1d5ab..dbaace585 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -1,15 +1,14 @@ GENFILES += frontends/verilog/verilog_parser.tab.cc -GENFILES += frontends/verilog/verilog_parser.tab.h +GENFILES += frontends/verilog/verilog_parser.tab.hh GENFILES += frontends/verilog/verilog_parser.output GENFILES += frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $< - $(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc + $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $< -frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc +frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l $(Q) mkdir -p $(dir $@) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 0134416c1..83921bf0b 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -42,7 +42,7 @@ #include "kernel/log.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/ast/ast.h" -#include "verilog_parser.tab.h" +#include "verilog_parser.tab.hh" USING_YOSYS_NAMESPACE using namespace AST;