riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

This commit is contained in:
Eddie Hung 2019-07-15 12:03:51 -07:00
parent d032198fac
commit 5fb27c071b
7 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/ice40/abc_hx.box
View File

@ -8,6 +8,6 @@
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_CARRY_LUT4 1 1 3 2 $__ICE40_FULL_ADDER 1 1 3 2
400 379 316 400 379 316
259 231 126 259 231 126

2
techlibs/ice40/abc_lp.box
View File

@ -8,6 +8,6 @@
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_CARRY_LUT4 1 1 3 2 $__ICE40_FULL_ADDER 1 1 3 2
589 558 465 589 558 465
675 609 186 675 609 186

2
techlibs/ice40/abc_u.box
View File

@ -8,6 +8,6 @@
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_CARRY_LUT4 1 1 3 2 $__ICE40_FULL_ADDER 1 1 3 2
1231 1205 874 1231 1205 874
675 609 278 675 609 278

2
techlibs/ice40/arith_map.v
View File

@ -45,7 +45,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
`ifdef _ABC `ifdef _ABC
\$__ICE40_CARRY_LUT4 carry ( \$__ICE40_FULL_ADDER carry (
.A(AA[i]), .A(AA[i]),
.B(BB[i]), .B(BB[i]),
.CI(C[i]), .CI(C[i]),

2
techlibs/ice40/cells_map.v
View File

@ -63,7 +63,7 @@ endmodule
`endif `endif
`ifdef _ABC `ifdef _ABC
module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI); module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
SB_CARRY carry ( SB_CARRY carry (
.I0(A), .I0(A),
.I1(B), .I1(B),

2
techlibs/ice40/cells_sim.v
View File

@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI); module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
SB_CARRY carry ( SB_CARRY carry (
.I0(A), .I0(A),
.I1(B), .I1(B),

4
techlibs/ice40/ice40_opt.cc
View File

@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
continue; continue;
} }
if (cell->type == "$__ICE40_CARRY_LUT4") if (cell->type == "$__ICE40_FULL_ADDER")
{ {
SigSpec non_const_inputs, replacement_output; SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0; int count_zeros = 0, count_ones = 0;
@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output); module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n", log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut"; cell->type = "$lut";
cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });