mirror of https://github.com/YosysHQ/yosys.git
Move Verific SVA importer to extra C++ source file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
c4bf34f6ce
commit
5fa2aa2741
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@ -3,6 +3,8 @@ OBJS += frontends/verific/verific.o
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ifeq ($(ENABLE_VERIFIC),1)
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ifeq ($(ENABLE_VERIFIC),1)
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OBJS += frontends/verific/verificsva.o
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EXTRA_TARGETS += share/verific
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EXTRA_TARGETS += share/verific
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share/verific:
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share/verific:
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,79 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifdef YOSYS_ENABLE_VERIFIC
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#include "DataBase.h"
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YOSYS_NAMESPACE_BEGIN
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extern pool<int> verific_sva_prims;
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struct VerificImporter;
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struct VerificClockEdge {
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Verific::Net *clock_net = nullptr;
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SigBit clock_sig = State::Sx;
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bool posedge = false;
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VerificClockEdge(VerificImporter *importer, Verific::Instance *inst);
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};
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struct VerificImporter
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{
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RTLIL::Module *module;
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Verific::Netlist *netlist;
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std::map<Verific::Net*, RTLIL::SigBit> net_map;
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std::map<Verific::Net*, Verific::Net*> sva_posedge_map;
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bool mode_gates, mode_keep, mode_nosva, mode_nosvapp, mode_names, verbose;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_nosvapp, bool mode_names, bool verbose);
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RTLIL::SigBit net_map_at(Verific::Net *net);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj);
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RTLIL::SigSpec operatorInput(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
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RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
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RTLIL::SigSpec operatorOutput(Verific::Instance *inst);
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bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);
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bool import_netlist_instance_cells(Verific::Instance *inst, RTLIL::IdString inst_name);
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void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol);
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void merge_past_ffs(pool<RTLIL::Cell*> &candidates);
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void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo);
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};
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void import_sva_assert(VerificImporter *importer, Verific::Instance *inst);
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void import_sva_assume(VerificImporter *importer, Verific::Instance *inst);
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void import_sva_cover(VerificImporter *importer, Verific::Instance *inst);
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void svapp_assert(Verific::Instance *inst);
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void svapp_assume(Verific::Instance *inst);
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void svapp_cover(Verific::Instance *inst);
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YOSYS_NAMESPACE_END
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#endif
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@ -0,0 +1,384 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "frontends/verific/verific.h"
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USING_YOSYS_NAMESPACE
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#ifdef VERIFIC_NAMESPACE
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using namespace Verific;
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#endif
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YOSYS_NAMESPACE_BEGIN
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struct VerificSvaImporter
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{
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VerificImporter *importer = nullptr;
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Module *module = nullptr;
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Netlist *netlist = nullptr;
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Instance *root = nullptr;
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SigBit clock = State::Sx;
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bool clock_posedge = false;
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SigBit disable_iff = State::S0;
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bool mode_assert = false;
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bool mode_assume = false;
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bool mode_cover = false;
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bool eventually = false;
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bool did_something = false;
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Instance *net_to_ast_driver(Net *n)
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{
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if (n == nullptr)
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return nullptr;
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if (n->IsMultipleDriven())
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return nullptr;
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Instance *inst = n->Driver();
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if (inst == nullptr)
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return nullptr;
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if (!verific_sva_prims.count(inst->Type()))
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return nullptr;
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if (inst->Type() == PRIM_SVA_ROSE || inst->Type() == PRIM_SVA_FELL ||
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inst->Type() == PRIM_SVA_STABLE || inst->Type() == OPER_SVA_STABLE || inst->Type() == PRIM_SVA_PAST)
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return nullptr;
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return inst;
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}
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Instance *get_ast_input(Instance *inst) { return net_to_ast_driver(inst->GetInput()); }
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Instance *get_ast_input1(Instance *inst) { return net_to_ast_driver(inst->GetInput1()); }
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Instance *get_ast_input2(Instance *inst) { return net_to_ast_driver(inst->GetInput2()); }
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Instance *get_ast_input3(Instance *inst) { return net_to_ast_driver(inst->GetInput3()); }
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Instance *get_ast_control(Instance *inst) { return net_to_ast_driver(inst->GetControl()); }
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// ----------------------------------------------------------
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// SVA Preprocessor
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Net *rewrite_input(Instance *inst) { return rewrite(get_ast_input(inst), inst->GetInput()); }
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Net *rewrite_input1(Instance *inst) { return rewrite(get_ast_input1(inst), inst->GetInput1()); }
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Net *rewrite_input2(Instance *inst) { return rewrite(get_ast_input2(inst), inst->GetInput2()); }
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Net *rewrite_input3(Instance *inst) { return rewrite(get_ast_input3(inst), inst->GetInput3()); }
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Net *rewrite_control(Instance *inst) { return rewrite(get_ast_control(inst), inst->GetControl()); }
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Net *rewrite(Instance *inst, Net *default_net = nullptr)
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{
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if (inst == nullptr)
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return default_net;
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if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_ASSUME ||
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inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME) {
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Net *new_net = rewrite(get_ast_input(inst));
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if (new_net) {
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inst->Disconnect(inst->View()->GetInput());
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inst->Connect(inst->View()->GetInput(), new_net);
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}
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return default_net;
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}
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if (inst->Type() == PRIM_SVA_AT || inst->Type() == PRIM_SVA_DISABLE_IFF) {
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Net *new_net = rewrite(get_ast_input2(inst));
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if (new_net) {
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inst->Disconnect(inst->View()->GetInput2());
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inst->Connect(inst->View()->GetInput2(), new_net);
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}
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return default_net;
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}
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if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
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{
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if (mode_cover) {
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did_something = true;
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Net *new_in1 = rewrite_input1(inst);
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Net *new_in2 = rewrite_input2(inst);
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return netlist->SvaBinary(PRIM_SVA_SEQ_CONCAT, new_in1, new_in2, inst->Linefile());
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}
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return default_net;
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}
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if (inst->Type() == PRIM_SVA_NOT)
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{
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if (mode_assert || mode_assume) {
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did_something = true;
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Net *new_in = rewrite_input(inst);
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Net *net_zero = netlist->Gnd(inst->Linefile());
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return netlist->SvaBinary(PRIM_SVA_OVERLAPPED_IMPLICATION, new_in, net_zero, inst->Linefile());
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}
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return default_net;
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}
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return default_net;
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}
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void rewrite()
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{
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netlist = root->Owner();
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do {
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did_something = false;
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rewrite(root);
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} while (did_something);
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}
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// ----------------------------------------------------------
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// SVA Importer
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struct sequence_t {
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int length = 0;
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SigBit sig_a = State::S1;
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SigBit sig_en = State::S1;
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};
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void sequence_cond(sequence_t &seq, SigBit cond)
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{
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seq.sig_a = module->And(NEW_ID, seq.sig_a, cond);
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}
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void sequence_ff(sequence_t &seq)
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{
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if (disable_iff != State::S0)
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seq.sig_en = module->Mux(NEW_ID, seq.sig_en, State::S0, disable_iff);
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Wire *sig_a_q = module->addWire(NEW_ID);
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sig_a_q->attributes["\\init"] = Const(0, 1);
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Wire *sig_en_q = module->addWire(NEW_ID);
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sig_en_q->attributes["\\init"] = Const(0, 1);
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module->addDff(NEW_ID, clock, seq.sig_a, sig_a_q, clock_posedge);
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module->addDff(NEW_ID, clock, seq.sig_en, sig_en_q, clock_posedge);
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seq.length++;
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seq.sig_a = sig_a_q;
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seq.sig_en = sig_en_q;
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}
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void parse_sequence(sequence_t &seq, Net *n)
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{
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Instance *inst = net_to_ast_driver(n);
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// Regular expression
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if (inst == nullptr) {
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sequence_cond(seq, importer->net_map_at(n));
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return;
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}
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// SVA Primitives
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
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{
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parse_sequence(seq, inst->GetInput1());
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seq.sig_en = module->And(NEW_ID, seq.sig_en, seq.sig_a);
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sequence_ff(seq);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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if (inst->Type() == PRIM_SVA_SEQ_CONCAT)
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{
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int sva_low = atoi(inst->GetAttValue("sva:low"));
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int sva_high = atoi(inst->GetAttValue("sva:low"));
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if (sva_low != sva_high)
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log_error("Ranges on SVA sequence concatenation operator are not supported at the moment.\n");
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parse_sequence(seq, inst->GetInput1());
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for (int i = 0; i < sva_low; i++)
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sequence_ff(seq);
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parse_sequence(seq, inst->GetInput2());
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return;
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}
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if (inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT)
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{
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int sva_low = atoi(inst->GetAttValue("sva:low"));
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int sva_high = atoi(inst->GetAttValue("sva:low"));
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if (sva_low != sva_high)
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log_error("Ranges on SVA consecutive repeat operator are not supported at the moment.\n");
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parse_sequence(seq, inst->GetInput());
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for (int i = 1; i < sva_low; i++) {
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sequence_ff(seq);
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parse_sequence(seq, inst->GetInput());
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}
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return;
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}
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// Handle unsupported primitives
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if (!importer->mode_keep)
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log_error("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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log_warning("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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}
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void import()
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{
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module = importer->module;
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netlist = root->Owner();
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RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID);
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// parse SVA property clock event
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Instance *at_node = get_ast_input(root);
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// asynchronous immediate assertion/assumption/cover
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if (at_node == nullptr && (root->Type() == PRIM_SVA_IMMEDIATE_ASSERT ||
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root->Type() == PRIM_SVA_IMMEDIATE_COVER || root->Type() == PRIM_SVA_IMMEDIATE_ASSUME))
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{
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SigSpec sig_a = importer->net_map_at(root->GetInput());
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RTLIL::Cell *c = nullptr;
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if (eventually) {
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if (mode_assert) c = module->addLive(root_name, sig_a, State::S1);
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if (mode_assume) c = module->addFair(root_name, sig_a, State::S1);
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} else {
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if (mode_assert) c = module->addAssert(root_name, sig_a, State::S1);
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if (mode_assume) c = module->addAssume(root_name, sig_a, State::S1);
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if (mode_cover) c = module->addCover(root_name, sig_a, State::S1);
|
||||||
|
}
|
||||||
|
|
||||||
|
importer->import_attributes(c->attributes, root);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
log_assert(at_node && at_node->Type() == PRIM_SVA_AT);
|
||||||
|
|
||||||
|
VerificClockEdge clock_edge(importer, get_ast_input1(at_node));
|
||||||
|
clock = clock_edge.clock_sig;
|
||||||
|
clock_posedge = clock_edge.posedge;
|
||||||
|
|
||||||
|
// parse disable_iff expression
|
||||||
|
|
||||||
|
Net *sequence_net = at_node->GetInput2();
|
||||||
|
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
Instance *sequence_node = net_to_ast_driver(sequence_net);
|
||||||
|
|
||||||
|
if (sequence_node && sequence_node->Type() == PRIM_SVA_S_EVENTUALLY) {
|
||||||
|
eventually = true;
|
||||||
|
sequence_net = sequence_node->GetInput();
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sequence_node && sequence_node->Type() == PRIM_SVA_DISABLE_IFF) {
|
||||||
|
disable_iff = importer->net_map_at(sequence_node->GetInput1());
|
||||||
|
sequence_net = sequence_node->GetInput2();
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// parse SVA sequence into trigger signal
|
||||||
|
|
||||||
|
sequence_t seq;
|
||||||
|
parse_sequence(seq, sequence_net);
|
||||||
|
sequence_ff(seq);
|
||||||
|
|
||||||
|
// generate assert/assume/cover cell
|
||||||
|
|
||||||
|
RTLIL::Cell *c = nullptr;
|
||||||
|
|
||||||
|
if (eventually) {
|
||||||
|
if (mode_assert) c = module->addLive(root_name, seq.sig_a, seq.sig_en);
|
||||||
|
if (mode_assume) c = module->addFair(root_name, seq.sig_a, seq.sig_en);
|
||||||
|
} else {
|
||||||
|
if (mode_assert) c = module->addAssert(root_name, seq.sig_a, seq.sig_en);
|
||||||
|
if (mode_assume) c = module->addAssume(root_name, seq.sig_a, seq.sig_en);
|
||||||
|
if (mode_cover) c = module->addCover(root_name, seq.sig_a, seq.sig_en);
|
||||||
|
}
|
||||||
|
|
||||||
|
importer->import_attributes(c->attributes, root);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
void svapp_assert(Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_assert = true;
|
||||||
|
worker.rewrite();
|
||||||
|
}
|
||||||
|
|
||||||
|
void svapp_assume(Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_assume = true;
|
||||||
|
worker.rewrite();
|
||||||
|
}
|
||||||
|
|
||||||
|
void svapp_cover(Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_cover = true;
|
||||||
|
worker.rewrite();
|
||||||
|
}
|
||||||
|
|
||||||
|
void import_sva_assert(VerificImporter *importer, Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.importer = importer;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_assert = true;
|
||||||
|
worker.import();
|
||||||
|
}
|
||||||
|
|
||||||
|
void import_sva_assume(VerificImporter *importer, Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.importer = importer;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_assume = true;
|
||||||
|
worker.import();
|
||||||
|
}
|
||||||
|
|
||||||
|
void import_sva_cover(VerificImporter *importer, Instance *inst)
|
||||||
|
{
|
||||||
|
VerificSvaImporter worker;
|
||||||
|
worker.importer = importer;
|
||||||
|
worker.root = inst;
|
||||||
|
worker.mode_cover = true;
|
||||||
|
worker.import();
|
||||||
|
}
|
||||||
|
|
||||||
|
YOSYS_NAMESPACE_END
|
||||||
Loading…
Reference in New Issue