mirror of https://github.com/YosysHQ/yosys.git
Start new write_xaiger2 backend for export w/ boxes
This commit is contained in:
Martin Povišer
parent
ea765686b6
commit
5f8d7ff170
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@ -700,13 +700,14 @@ struct AigerWriter : Index<AigerWriter, unsigned int> {
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char buf[128];
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snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n",
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ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands);
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f->seekp(0);
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f->write(buf, strlen(buf));
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}
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void write(std::ostream *f) {
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reset_counters();
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auto file_start = f->tellp();
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// populate inputs
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std::vector<SigBit> inputs;
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for (auto id : top->ports) {
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@ -750,6 +751,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int> {
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auto data_end = f->tellp();
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// revisit header and the list of outputs
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f->seekp(file_start);
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write_header();
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for (auto pair : outputs) {
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char buf[16];
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@ -788,6 +790,390 @@ struct AigerWriter : Index<AigerWriter, unsigned int> {
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}
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};
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struct XAigerWriter : AigerWriter {
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XAigerWriter()
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{
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allow_blackboxes = true;
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}
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bool mapping_prep = false;
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pool<Wire *> keep_wires;
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std::ofstream map_file;
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typedef std::pair<SigBit, HierCursor> HierBit;
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std::vector<HierBit> pos;
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std::vector<HierBit> pis;
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int proper_pos_counter = 0;
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pool<SigBit> driven_by_opaque_box;
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void ensure_pi(SigBit bit, HierCursor cursor={},
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bool box_port=false)
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{
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Lit &lit = pi_literal(bit, &cursor);
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if (lit == EMPTY_LIT) {
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lit = lit_counter;
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pis.push_back(std::make_pair(bit, cursor));
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lit_counter += 2;
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if (map_file.is_open() && !box_port) {
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log_assert(cursor.is_top()); // TODO
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driven_by_opaque_box.insert(bit);
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map_file << "pi " << pis.size() - 1 << " " << bit.offset
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<< " " << bit.wire->name.c_str() << "\n";
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}
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} else {
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log_assert(!box_port);
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}
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}
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bool is_pi(SigBit bit, HierCursor cursor={})
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{
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return pi_literal(bit, &cursor) != EMPTY_LIT;
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}
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void pad_pi()
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{
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pis.push_back(std::make_pair(RTLIL::Sx, HierCursor{}));
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lit_counter += 2;
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}
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void append_box_ports(Cell *box, HierCursor &cursor, bool inputs)
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{
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for (auto &conn : box->connections_) {
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bool is_input = box->input(conn.first);
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bool is_output = box->output(conn.first);
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if (!(is_input || is_output) || (is_input && is_output))
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log_error("Ambiguous port direction on %s/%s\n",
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log_id(box->type), log_id(conn.first));
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if (is_input && inputs) {
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int bitp = 0;
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for (auto bit : conn.second) {
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if (!bit.wire) {
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bitp++;
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continue;
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}
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if (map_file.is_open()) {
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log_assert(cursor.is_top());
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map_file << "pseudopo " << proper_pos_counter++ << " " << bitp
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<< " " << box->name.c_str()
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<< " " << conn.first.c_str() << "\n";
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}
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pos.push_back(std::make_pair(bit, cursor));
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if (mapping_prep)
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conn.second[bitp] = RTLIL::Sx;
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bitp++;
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}
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} else if (is_output && !inputs) {
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for (auto &bit : conn.second) {
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if (!bit.wire || bit.wire->port_input)
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log_error("Bad connection");
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ensure_pi(bit, cursor);
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keep_wires.insert(bit.wire);
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}
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}
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}
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}
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RTLIL::Module *holes_module;
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std::stringstream h_buffer;
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static void write_be32(std::ostream &buffer, uint32_t u32)
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{
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typedef unsigned char uchar;
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unsigned char u32_be[4] = {
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(uchar) (u32 >> 24), (uchar) (u32 >> 16), (uchar) (u32 >> 8), (uchar) u32
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};
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buffer.write((char *) u32_be, sizeof(u32_be));
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}
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void prep_boxes(int pending_pos_num)
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{
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// boxes which have timing data, maybe a whitebox model
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std::vector<std::tuple<HierCursor, Cell *, Module *>> nonopaque_boxes;
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// boxes which are fully opaque
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std::vector<std::tuple<HierCursor, Cell *, Module *>> opaque_boxes;
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log_debug("found boxes:\n");
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visit_hierarchy([&](HierCursor &cursor) {
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auto &minfo = cursor.leaf_minfo(*this);
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for (auto box : minfo.found_blackboxes) {
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log_debug(" - %s.%s (type %s): ", cursor.path().c_str(),
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RTLIL::unescape_id(box->name).c_str(),
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log_id(box->type));
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Module *box_module = design->module(box->type), *box_derived;
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if (box_module && !box->parameters.empty()) {
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// TODO: This is potentially costly even if a cached derivation exists
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box_derived = design->module(box_module->derive(design, box->parameters));
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log_assert(box_derived);
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} else {
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box_derived = box_module;
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}
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if (box_derived && box_derived->has_attribute(ID::abc9_box_id)) {
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// This is an ABC9 box, we have timing data, maybe even a whitebox model
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// These need to go last in the AIGER port list.
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nonopaque_boxes.push_back(std::make_tuple(cursor, box, box_derived));
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log_debug("non-opaque\n");
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} else {
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opaque_boxes.push_back(std::make_tuple(cursor, box, box_derived));
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log_debug("opaque\n");
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}
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}
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});
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for (auto [cursor, box, def] : opaque_boxes)
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append_box_ports(box, cursor, true);
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holes_module = design->addModule(NEW_ID);
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std::vector<RTLIL::Wire *> holes_pis;
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int boxes_ci_num = 0, boxes_co_num = 0;
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int box_seq = 0;
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for (auto [cursor, box, def] : nonopaque_boxes) {
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// use `def->name` not `box->type` as we want the derived type
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Cell *holes_wb = holes_module->addCell(NEW_ID, def->name);
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int holes_pi_idx = 0;
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if (map_file.is_open()) {
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log_assert(cursor.is_top());
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map_file << "box " << box_seq << " " << box->name.c_str() << "\n";
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}
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box_seq++;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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log_assert(port);
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SigSpec conn = box->hasPort(port_id) ? box->getPort(port_id) : SigSpec{};
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if (port->port_input && !port->port_output) {
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// primary
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for (int i = 0; i < port->width; i++) {
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SigBit bit;
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if (i < conn.size()) {
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bit = conn[i];
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} else {
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// FIXME: hierarchical path
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log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
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log_id(port_id), i, log_id(box), log_id(box->type));
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bit = RTLIL::Sx;
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}
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pos.push_back(std::make_pair(bit, cursor));
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}
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boxes_co_num += port->width;
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if (mapping_prep && !conn.empty())
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box->setPort(port_id, SigSpec(RTLIL::Sx, conn.size()));
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// holes
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SigSpec in_conn;
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for (int i = 0; i < port->width; i++) {
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while (holes_pi_idx >= (int) holes_pis.size()) {
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Wire *w = holes_module->addWire(NEW_ID, 1);
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w->port_input = true;
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holes_module->ports.push_back(w->name);
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holes_pis.push_back(w);
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}
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in_conn.append(holes_pis[i]);
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holes_pi_idx++;
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}
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holes_wb->setPort(port_id, in_conn);
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} else if (port->port_output && !port->port_input) {
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// primary
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for (int i = 0; i < port->width; i++) {
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SigBit bit;
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if (i < conn.size() && conn[i].is_wire()) {
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bit = conn[i];
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} else {
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// FIXME: hierarchical path
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log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
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log_id(port_id), i, log_id(box), log_id(box->type));
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pad_pi();
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continue;
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}
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ensure_pi(bit, cursor, true);
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keep_wires.insert(bit.wire);
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}
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boxes_ci_num += port->width;
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// holes
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Wire *w = holes_module->addWire(NEW_ID, port->width);
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w->port_output = true;
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holes_module->ports.push_back(w->name);
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holes_wb->setPort(port_id, w);
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} else {
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log_error("Ambiguous port direction on %s/%s\n",
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log_id(box->type), log_id(port_id));
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}
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}
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}
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for (auto [cursor, box, def] : opaque_boxes)
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append_box_ports(box, cursor, false);
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write_be32(h_buffer, 1);
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write_be32(h_buffer, pis.size());
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log_debug("ciNum = %zu\n", pis.size());
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write_be32(h_buffer, pending_pos_num + pos.size());
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log_debug("coNum = %zu\n", boxes_co_num + pos.size());
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write_be32(h_buffer, pis.size() - boxes_ci_num);
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log_debug("piNum = %zu\n", pis.size() - boxes_ci_num);
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write_be32(h_buffer, pending_pos_num + pos.size() - boxes_co_num);
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log_debug("poNum = %zu\n", pending_pos_num + pos.size() - boxes_co_num);
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write_be32(h_buffer, nonopaque_boxes.size());
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box_seq = 0;
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for (auto [cursor, box, def] : nonopaque_boxes) {
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int box_ci_num = 0, box_co_num = 0;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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log_assert(port);
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if (port->port_input && !port->port_output) {
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box_co_num += port->width;
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} else if (port->port_output && !port->port_input) {
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box_ci_num += port->width;
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} else {
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log_abort();
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}
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}
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write_be32(h_buffer, box_co_num);
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write_be32(h_buffer, box_ci_num);
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write_be32(h_buffer, def->attributes.at(ID::abc9_box_id).as_int());
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write_be32(h_buffer, box_seq++);
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}
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}
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void clear_boxes()
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{
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design->remove(holes_module);
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}
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void write(std::ostream *f) {
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reset_counters();
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for (auto w : top->wires())
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if (w->port_input)
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for (int i = 0; i < w->width; i++)
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ensure_pi(SigBit(w, i));
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int proper_po_num = 0;
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for (auto w : top->wires())
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if (w->port_output)
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proper_po_num += w->width;
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prep_boxes(proper_po_num);
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for (auto w : top->wires())
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if (w->port_output)
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for (int i = 0; i < w->width; i++) {
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if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) {
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map_file << "po " << proper_pos_counter++ << " " << i
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<< " " << w->name.c_str() << "\n";
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}
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pos.push_back(std::make_pair(SigBit(w, i), HierCursor{}));
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}
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this->f = f;
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// start with the header
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ninputs = pis.size();
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noutputs = pos.size();
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write_header();
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// insert padding where output literals will go (once known)
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for (auto _ : pos) {
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", 0);
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f->write(buf, strlen(buf));
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}
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auto data_start = f->tellp();
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// now the guts
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std::vector<Lit> outlits;
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for (auto &pair : pos)
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outlits.push_back(eval_po(pair.first, &pair.second));
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// revisit header and the list of outputs
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f->seekp(0);
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ninputs = pis.size();
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noutputs = pos.size();
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write_header();
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for (auto lit : outlits) {
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", lit);
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f->write(buf, strlen(buf));
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}
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// double check we arrived at the same offset for the
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// main data section
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log_assert(data_start == f->tellp());
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// extensions
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f->seekp(0, std::ios::end);
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f->put('c');
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// insert empty 'r' and 's' sections (abc crashes if we provide 'a' without those)
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f->put('r');
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write_be32(*f, 4);
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write_be32(*f, 0);
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f->put('s');
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write_be32(*f, 4);
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write_be32(*f, 0);
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f->put('h');
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// TODO: get rid of std::string copy
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std::string h_buffer_str = h_buffer.str();
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write_be32(*f, h_buffer_str.size());
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f->write(h_buffer_str.data(), h_buffer_str.size());
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#if 1
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f->put('a');
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write_be32(*f, 0); // size to be filled later
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auto holes_aiger_start = f->tellp();
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{
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AigerWriter holes_writer;
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holes_writer.flatten = true;
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holes_writer.inline_whiteboxes = true;
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holes_writer.setup(holes_module);
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holes_writer.write(f);
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}
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auto holes_aiger_size = f->tellp() - holes_aiger_start;
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f->seekp(holes_aiger_start, std::ios::beg);
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f->seekp(-4, std::ios::cur);
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write_be32(*f, holes_aiger_size);
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#endif
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f->seekp(0, std::ios::end);
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if (mapping_prep) {
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std::vector<Cell *> to_remove_cells;
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for (auto cell : top->cells())
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if (!top_minfo->found_blackboxes.count(cell))
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to_remove_cells.push_back(cell);
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for (auto cell : to_remove_cells)
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top->remove(cell);
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pool<Wire *> to_remove;
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for (auto wire : top->wires())
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if (!wire->port_input && !wire->port_output && !keep_wires.count(wire))
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to_remove.insert(wire);
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top->remove(to_remove);
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}
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clear_boxes();
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}
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};
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struct Aiger2Backend : Backend {
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Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)")
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{
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@ -872,6 +1258,57 @@ struct Aiger2Backend : Backend {
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}
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} Aiger2Backend;
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struct XAiger2Backend : Backend {
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XAiger2Backend() : Backend("xaiger2", "write design to XAIGER file (new)")
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{
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experimental();
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, Design *design) override
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{
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log_header(design, "Executing XAIGER2 backend.\n");
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size_t argidx;
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XAigerWriter writer;
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std::string map_filename;
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writer.const_folding = true;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-strash")
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writer.strashing = true;
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else if (args[argidx] == "-flatten")
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writer.flatten = true;
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else if (args[argidx] == "-mapping_prep")
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writer.mapping_prep = true;
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else if (args[argidx] == "-map2" && argidx + 1 < args.size())
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map_filename = args[++argidx];
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else
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break;
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}
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extra_args(f, filename, args, argidx);
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Module *top = design->top_module();
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if (!top || !design->selected_whole_module(top))
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log_cmd_error("No top module selected\n");
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if (!map_filename.empty()) {
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writer.map_file.open(map_filename);
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if (!writer.map_file)
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log_cmd_error("Failed to open '%s' for writing\n", map_filename.c_str());
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}
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design->bufNormalize(true);
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writer.setup(top);
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writer.write(f);
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||||
|
||||
// we are leaving the sacred land, un-bufnormalize
|
||||
// (if not, this will lead to bugs: the buf-normalized
|
||||
// flag must not be kept on past the code that can work
|
||||
// with it)
|
||||
design->bufNormalize(false);
|
||||
}
|
||||
} XAiger2Backend;
|
||||
|
||||
struct AIGCounter : Index<AIGCounter, int> {
|
||||
typedef int Lit;
|
||||
const static Lit CONST_FALSE = -1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue