Merge pull request #4003 from povik/pp3-test-fix

quicklogic: Fix pp3 `dffs` test
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Lofty 2023-10-17 12:25:09 +01:00 committed by GitHub
commit 5f78d1d03e
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1 changed files with 17 additions and 4 deletions

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@ -7,14 +7,27 @@ hierarchy -top my_dff
proc proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd my_dff # Constrain all select calls below inside the top module
select -assert-none t:* select -assert-count 1 t:ckpad
select -assert-count 1 t:dffepc
select -assert-count 1 t:inpad
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1
select -assert-count 1 t:outpad
select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D
design -load read design -load read
hierarchy -top my_dffe hierarchy -top my_dffe
proc proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd my_dffe # Constrain all select calls below inside the top module
select -assert-none t:* select -assert-count 1 t:ckpad
select -assert-count 1 t:dffepc
select -assert-count 2 t:inpad
select -assert-count 1 t:logic_0
select -assert-count 1 t:outpad
select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D