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Merge pull request #4003 from povik/pp3-test-fix
quicklogic: Fix pp3 `dffs` test
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commit
5f78d1d03e
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@ -7,14 +7,27 @@ hierarchy -top my_dff
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proc
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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cd my_dff # Constrain all select calls below inside the top module
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select -assert-none t:*
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select -assert-count 1 t:ckpad
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:inpad
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 1 t:outpad
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select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D
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design -load read
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design -load read
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hierarchy -top my_dffe
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hierarchy -top my_dffe
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proc
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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cd my_dffe # Constrain all select calls below inside the top module
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select -assert-none t:*
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select -assert-count 1 t:ckpad
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select -assert-count 1 t:dffepc
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select -assert-count 2 t:inpad
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:outpad
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select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D
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