mirror of https://github.com/YosysHQ/yosys.git
Add read_verilog anyseq/anyconst/allseq/allconst attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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278685b084
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5ea2c53604
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@ -933,11 +933,43 @@ wire_name_list:
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wire_name_and_opt_assign:
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wire_name {
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if (current_wire_rand) {
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bool attr_anyconst = false;
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bool attr_anyseq = false;
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bool attr_allconst = false;
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bool attr_allseq = false;
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if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
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delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
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ast_stack.back()->children.back()->attributes.erase("\\anyconst");
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attr_anyconst = true;
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}
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if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
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delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
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ast_stack.back()->children.back()->attributes.erase("\\anyseq");
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attr_anyseq = true;
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}
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if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
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delete ast_stack.back()->children.back()->attributes.at("\\allconst");
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ast_stack.back()->children.back()->attributes.erase("\\allconst");
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attr_allconst = true;
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}
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if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
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delete ast_stack.back()->children.back()->attributes.at("\\allseq");
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ast_stack.back()->children.back()->attributes.erase("\\allseq");
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attr_allseq = true;
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}
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if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
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AstNode *wire = new AstNode(AST_IDENTIFIER);
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AstNode *fcall = new AstNode(AST_FCALL);
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wire->str = ast_stack.back()->children.back()->str;
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fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
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if (attr_anyconst)
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fcall->str = "\\$anyconst";
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if (attr_anyseq)
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fcall->str = "\\$anyseq";
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if (attr_allconst)
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fcall->str = "\\$allconst";
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if (attr_allseq)
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fcall->str = "\\$allseq";
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fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
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ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
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}
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