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Added $dffe support to write_verilog

This commit is contained in:
Clifford Wolf 2014-12-20 00:03:20 +01:00
parent bacd3699b3
commit 5df192e71c
1 changed files with 14 additions and 3 deletions
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17
backends/verilog/verilog_backend.cc
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@ -664,10 +664,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$dff" || cell->type == "$adff") if (cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffe")
{ {
RTLIL::SigSpec sig_clk, sig_arst, val_arst; RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
bool pol_clk, pol_arst = false; bool pol_clk, pol_arst = false, pol_en = false;
sig_clk = cell->getPort("\\CLK"); sig_clk = cell->getPort("\\CLK");
pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
@ -678,6 +678,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]);
} }
if (cell->type == "$dffe") {
sig_en = cell->getPort("\\EN");
pol_en = cell->parameters["\\EN_POLARITY"].as_bool();
}
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
@ -702,6 +707,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" " else\n", indent.c_str()); f << stringf("%s" " else\n", indent.c_str());
} }
if (cell->type == "$dffe") {
f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
dump_sigspec(f, sig_en);
f << stringf(")\n");
}
f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str()); f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str());
dump_cell_expr_port(f, cell, "D", false); dump_cell_expr_port(f, cell, "D", false);
f << stringf(";\n"); f << stringf(";\n");