riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add "verific -L <int>" option 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-09-04 20:06:10 +02:00
parent 0b7a18470b
commit 5d9d22f66d
3 changed files with 16 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
frontends/verific/verific.cc
View File

@ -64,6 +64,7 @@ YOSYS_NAMESPACE_BEGIN
int verific_verbose; int verific_verbose;
bool verific_import_pending; bool verific_import_pending;
string verific_error_msg; string verific_error_msg;
int verific_sva_fsm_limit;
vector<string> verific_incdirs, verific_libdirs; vector<string> verific_incdirs, verific_libdirs;
@ -1618,6 +1619,8 @@ struct VerificExtNets
void verific_import(Design *design, std::string top) void verific_import(Design *design, std::string top)
{ {
verific_sva_fsm_limit = 16;
std::set<Netlist*> nl_todo, nl_done; std::set<Netlist*> nl_todo, nl_done;
{ {
@ -1789,6 +1792,9 @@ struct VerificPass : public Pass {
log(" -nosva\n"); log(" -nosva\n");
log(" Ignore SVA properties, do not infer checker logic.\n"); log(" Ignore SVA properties, do not infer checker logic.\n");
log("\n"); log("\n");
log(" -L <int>\n");
log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
log("\n");
log(" -n\n"); log(" -n\n");
log(" Keep all Verific names on instances and nets. By default only\n"); log(" Keep all Verific names on instances and nets. By default only\n");
log(" user-declared names are preserved.\n"); log(" user-declared names are preserved.\n");
@ -1830,6 +1836,7 @@ struct VerificPass : public Pass {
} }
verific_verbose = 0; verific_verbose = 0;
verific_sva_fsm_limit = 16;
const char *release_str = Message::ReleaseString(); const char *release_str = Message::ReleaseString();
time_t release_time = Message::ReleaseDate(); time_t release_time = Message::ReleaseDate();
@ -2036,6 +2043,10 @@ struct VerificPass : public Pass {
mode_nosva = true; mode_nosva = true;
continue; continue;
} }
if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
verific_sva_fsm_limit = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-n") { if (args[argidx] == "-n") {
mode_names = true; mode_names = true;
continue; continue;

2
frontends/verific/verific.h
View File

@ -101,6 +101,8 @@ void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst
void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst); void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net); bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
extern int verific_sva_fsm_limit;
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END
#endif #endif

5
frontends/verific/verificsva.cc
View File

@ -466,13 +466,14 @@ struct SvaFsm
dnode.ctrl.sort_and_unify(); dnode.ctrl.sort_and_unify();
if (GetSize(dnode.ctrl) > 16) { if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) {
if (verific_verbose >= 2) { if (verific_verbose >= 2) {
log(" detected state explosion in DFSM generation:\n"); log(" detected state explosion in DFSM generation:\n");
dump(); dump();
log(" ctrl signal: %s\n", log_signal(dnode.ctrl)); log(" ctrl signal: %s\n", log_signal(dnode.ctrl));
} }
log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl)); log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n",
GetSize(dnode.ctrl), verific_sva_fsm_limit);
} }
for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++) for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)