mirror of https://github.com/YosysHQ/yosys.git
Progress on cell help messages
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255bb914ba
commit
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@ -644,7 +644,7 @@ struct HelpPass : public Pass {
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for (auto &it : cell_help_messages.cell_help) {
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for (auto &it : cell_help_messages.cell_help) {
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string line = split_tokens(it.second, "\n").at(0);
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string line = split_tokens(it.second, "\n").at(0);
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string cell_name = next_token(line);
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string cell_name = next_token(line);
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log(" %-10s %s\n", cell_name.c_str(), line.c_str());
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log(" %-15s %s\n", cell_name.c_str(), line.c_str());
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}
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}
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log("\n");
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log("\n");
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log("Type 'help <cell_type>' for more information on a cell type.\n");
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log("Type 'help <cell_type>' for more information on a cell type.\n");
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@ -6,6 +6,7 @@ import json
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current_help_msg = []
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current_help_msg = []
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current_module_code = []
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current_module_code = []
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current_module_name = None
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current_module_name = None
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current_module_signature = None
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def print_current_cell():
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def print_current_cell():
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print("cell_help[\"%s\"] = %s;" % (current_module_name, "\n".join([json.dumps(line) for line in current_help_msg])))
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print("cell_help[\"%s\"] = %s;" % (current_module_name, "\n".join([json.dumps(line) for line in current_help_msg])))
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@ -16,10 +17,18 @@ for line in fileinput.input():
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current_help_msg.append(line[4:] if len(line) > 4 else "\n")
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current_help_msg.append(line[4:] if len(line) > 4 else "\n")
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if line.startswith("module "):
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if line.startswith("module "):
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current_module_name = line.split()[1].strip("\\")
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current_module_name = line.split()[1].strip("\\")
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current_module_signature = " ".join(line.replace("\\", "").replace(";", "").split()[1:])
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current_module_code = []
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current_module_code = []
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current_module_code.append(line)
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elif not line.startswith("endmodule"):
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line = " " + line
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current_module_code.append(line.replace("\t", " "))
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if line.startswith("endmodule"):
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if line.startswith("endmodule"):
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if len(current_help_msg) > 0:
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if len(current_help_msg) == 0:
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current_help_msg.append("\n")
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current_help_msg.append(" %s\n" % current_module_signature)
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current_help_msg.append("\n")
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current_help_msg.append("No help message for this cell type found.\n")
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current_help_msg.append("\n")
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print_current_cell()
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print_current_cell()
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current_help_msg = []
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current_help_msg = []
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@ -504,7 +504,7 @@ endmodule
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//- Truth table: D C | Q
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//- Truth table: D C | Q
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//- -----+---
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//- -----+---
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//- d \ | d
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//- d \ | d
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//- - = | q
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//- - - | q
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//-
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//-
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module \$_DFF_N_ (D, Q, C);
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module \$_DFF_N_ (D, Q, C);
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input D, C;
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input D, C;
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@ -523,7 +523,7 @@ endmodule
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//- Truth table: D C | Q
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//- Truth table: D C | Q
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//- -----+---
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//- -----+---
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//- d / | d
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//- d / | d
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//- - = | q
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//- - - | q
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//-
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//-
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module \$_DFF_P_ (D, Q, C);
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module \$_DFF_P_ (D, Q, C);
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input D, C;
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input D, C;
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@ -533,6 +533,17 @@ always @(posedge C) begin
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end
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end
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endmodule
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_NN_ (D, C, E, Q)
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//-
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//- A negative edge D-type flip-flop with negative polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d \ 0 | d
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//- - - - | q
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//-
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module \$_DFFE_NN_ (D, Q, C, E);
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module \$_DFFE_NN_ (D, Q, C, E);
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input D, C, E;
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input D, C, E;
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output reg Q;
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output reg Q;
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@ -541,6 +552,17 @@ always @(negedge C) begin
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end
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end
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endmodule
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_NP_ (D, C, E, Q)
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//-
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//- A negative edge D-type flip-flop with positive polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d \ 1 | d
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//- - - - | q
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//-
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module \$_DFFE_NP_ (D, Q, C, E);
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module \$_DFFE_NP_ (D, Q, C, E);
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input D, C, E;
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input D, C, E;
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output reg Q;
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output reg Q;
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@ -549,6 +571,17 @@ always @(negedge C) begin
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end
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end
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endmodule
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_PN_ (D, C, E, Q)
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//-
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//- A positive edge D-type flip-flop with negative polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d / 0 | d
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//- - - - | q
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//-
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module \$_DFFE_PN_ (D, Q, C, E);
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module \$_DFFE_PN_ (D, Q, C, E);
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input D, C, E;
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input D, C, E;
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output reg Q;
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output reg Q;
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@ -557,6 +590,17 @@ always @(posedge C) begin
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end
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end
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endmodule
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_PP_ (D, C, E, Q)
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//-
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//- A positive edge D-type flip-flop with positive polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d / 1 | d
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//- - - - | q
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//-
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module \$_DFFE_PP_ (D, Q, C, E);
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module \$_DFFE_PP_ (D, Q, C, E);
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input D, C, E;
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input D, C, E;
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output reg Q;
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output reg Q;
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