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gatemate: Fix minor issues with `memory_libmap` (#3343)

This commit is contained in:
Patrick Urban 2022-05-27 23:35:26 +02:00 committed by GitHub
parent 197c9e04e8
commit 5d08688054
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 39 additions and 28 deletions
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4
techlibs/gatemate/brams.txt
View File

@ -34,8 +34,10 @@ ram block $__CC_BRAM_TDP_ {
}
portoption "WR_MODE" "WRITE_THROUGH" {
rdwr new;
wrtrans all new;
}
wrbe_separate;
optional_rw;
}
}
@ -61,6 +63,7 @@ ram block $__CC_BRAM_SDP_ {
}
clock anyedge;
clken;
optional;
}
port sw "W" {
option "MODE" "20K" {
@ -72,5 +75,6 @@ ram block $__CC_BRAM_SDP_ {
clock anyedge;
clken;
wrbe_separate;
optional;
}
}

63
techlibs/gatemate/brams_map.v
View File

@ -4,12 +4,16 @@ parameter INIT = 0;
parameter OPTION_MODE = "20K";
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_RD_USED = 1;
parameter PORT_A_WR_USED = 1;
parameter PORT_A_RD_WIDTH = 1;
parameter PORT_A_WR_WIDTH = 1;
parameter PORT_A_WR_BE_WIDTH = 1;
parameter PORT_A_OPTION_WR_MODE = "NO_CHANGE";
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_RD_USED = 1;
parameter PORT_B_WR_USED = 1;
parameter PORT_B_RD_WIDTH = 1;
parameter PORT_B_WR_WIDTH = 1;
parameter PORT_B_WR_BE_WIDTH = 1;
@ -98,10 +102,10 @@ generate
.INIT_3D(INIT['h3d*320+:320]),
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_WIDTH),
.A_WR_WIDTH(PORT_A_WR_WIDTH),
.B_RD_WIDTH(PORT_B_RD_WIDTH),
.B_WR_WIDTH(PORT_B_WR_WIDTH),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
@ -119,7 +123,7 @@ generate
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_A_WR_DATA),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),
.B_DO(PORT_B_RD_DATA),
);
@ -253,10 +257,10 @@ generate
.INIT_7D(INIT['h7d*320+:320]),
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_WIDTH),
.A_WR_WIDTH(PORT_A_WR_WIDTH),
.B_RD_WIDTH(PORT_B_RD_WIDTH),
.B_WR_WIDTH(PORT_B_WR_WIDTH),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
@ -274,7 +278,7 @@ generate
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_A_WR_DATA),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),
.B_DO(PORT_B_RD_DATA),
);
@ -409,10 +413,10 @@ generate
.INIT_7D(INIT['h7d*320+:320]),
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(PORT_A_RD_WIDTH),
.A_WR_WIDTH(PORT_A_WR_WIDTH),
.B_RD_WIDTH(PORT_B_RD_WIDTH),
.B_WR_WIDTH(PORT_B_WR_WIDTH),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
@ -432,7 +436,7 @@ generate
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_A_WR_DATA),
.B_DI(PORT_B_WR_DATA),
.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
);
CC_BRAM_40K #(
@ -564,10 +568,10 @@ generate
.INIT_7D(INIT['hfd*320+:320]),
.INIT_7E(INIT['hfe*320+:320]),
.INIT_7F(INIT['hff*320+:320]),
.A_RD_WIDTH(PORT_A_RD_WIDTH),
.A_WR_WIDTH(PORT_A_WR_WIDTH),
.B_RD_WIDTH(PORT_B_RD_WIDTH),
.B_WR_WIDTH(PORT_B_WR_WIDTH),
.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),
.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),
.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),
.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),
.RAM_MODE("TDP"),
.A_WR_MODE(PORT_A_OPTION_WR_MODE),
.B_WR_MODE(PORT_B_OPTION_WR_MODE),
@ -588,7 +592,7 @@ generate
.B_EN(PORT_B_CLK_EN),
.B_WE(PORT_B_WR_EN),
.B_BM(PORT_B_WR_BE),
.B_DI(PORT_A_WR_DATA),
.B_DI(PORT_B_WR_DATA),
.B_DO(PORT_B_RD_DATA),
.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
);
@ -602,12 +606,15 @@ module $__CC_BRAM_SDP_(...);
parameter INIT = 0;
parameter OPTION_MODE = "20K";
parameter OPTION_WR_MODE = "NO_CHANGE";
parameter PORT_W_CLK_POL = 1;
parameter PORT_W_USED = 1;
parameter PORT_W_WIDTH = 40;
parameter PORT_W_WR_BE_WIDTH = 40;
parameter PORT_R_CLK_POL = 1;
parameter PORT_R_USED = 1;
parameter PORT_R_WIDTH = 40;
input PORT_W_CLK;
@ -690,12 +697,12 @@ generate
.INIT_3E(INIT['h3e*320+:320]),
.INIT_3F(INIT['h3f*320+:320]),
.A_RD_WIDTH(0),
.A_WR_WIDTH(PORT_W_WIDTH),
.B_RD_WIDTH(PORT_R_WIDTH),
.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),
.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),
.B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE("NO_CHANGE"),
.B_WR_MODE("NO_CHANGE"),
.A_WR_MODE(OPTION_WR_MODE),
.B_WR_MODE(OPTION_WR_MODE),
.A_CLK_INV(!PORT_W_CLK_POL),
.B_CLK_INV(!PORT_R_CLK_POL),
) _TECHMAP_REPLACE_ (
@ -845,12 +852,12 @@ generate
.INIT_7E(INIT['h7e*320+:320]),
.INIT_7F(INIT['h7f*320+:320]),
.A_RD_WIDTH(0),
.A_WR_WIDTH(PORT_W_WIDTH),
.B_RD_WIDTH(PORT_R_WIDTH),
.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),
.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),
.B_WR_WIDTH(0),
.RAM_MODE("SDP"),
.A_WR_MODE("NO_CHANGE"),
.B_WR_MODE("NO_CHANGE"),
.A_WR_MODE(OPTION_WR_MODE),
.B_WR_MODE(OPTION_WR_MODE),
.A_CLK_INV(!PORT_W_CLK_POL),
.B_CLK_INV(!PORT_R_CLK_POL),
) _TECHMAP_REPLACE_ (