diff --git a/docs/source/cell/word_binary.rst b/docs/source/cell/word_binary.rst
index 5c802294c..87d558eda 100644
--- a/docs/source/cell/word_binary.rst
+++ b/docs/source/cell/word_binary.rst
@@ -14,8 +14,6 @@ Binary operators
    shiftx, div, mod, pmux (less-so) can produce 'x' output even if all inputs
    are defined
 
-.. todo:: `$eqx` is the case equality operator
-
 All binary RTL cells have two input ports ``A`` and ``B`` and one output port
 ``Y``. They also have the following parameters:
 
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a954b64ec..bf30443c5 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -833,10 +833,11 @@ endmodule
 //-     $eqx (A, B, Y)
 //* group binary
 //-
-//- An exact equality comparison between inputs 'A' and 'B'. 
-//- This corresponds to the Verilog '===' operator.
-//- Unlike equality comparison that can give 'x' as output, 
-//- an exact equality comparison will strictly give '0' or '1' as output.
+//- An exact equality comparison between inputs 'A' and 'B'. Also known as the
+//- case equality operator. This corresponds to the Verilog '===' operator.
+//- Unlike equality comparison that can give 'x' as output, an exact equality
+//- comparison will strictly give '0' or '1' as output, even if input includes
+//- 'x' or 'z' values.
 //-
 module \$eqx (A, B, Y);