mirror of https://github.com/YosysHQ/yosys.git
opt_clean: improve warning message
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@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
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goto next_wire;
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if (mapped_wire_bit != init[i]) {
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log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit));
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log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
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goto next_wire;
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}
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}
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@ -1,4 +1,4 @@
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logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
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logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
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logger -expect-no-warnings
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read_verilog <<EOT
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module top;
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