From b11cf67a8170ee830beedadc7156c4e83e4f1134 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 10:30:20 -0700 Subject: [PATCH 1/6] Setup tests/verilog properly --- Makefile | 1 + tests/verilog/.gitignore | 3 +++ tests/verilog/run-test.sh | 20 ++++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100644 tests/verilog/.gitignore create mode 100755 tests/verilog/run-test.sh diff --git a/Makefile b/Makefile index a481dd92b..cd6179879 100644 --- a/Makefile +++ b/Makefile @@ -780,6 +780,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/memfile && bash run-test.sh + +cd tests/verilog && bash run-test.sh @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/verilog/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/verilog/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk From e5ce5a4fd532f35cf8dd625b97aa426e4661e119 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 11:05:19 -0700 Subject: [PATCH 2/6] tests: add #2042 testcase --- tests/verilog/bug2042.ys | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/verilog/bug2042.ys diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys new file mode 100644 index 000000000..009e2c20c --- /dev/null +++ b/tests/verilog/bug2042.ys @@ -0,0 +1,12 @@ +logger -expect error "Non-ANSI style task/function arguments not currently supported" 1 +read_verilog < Date: Mon, 11 May 2020 13:00:36 -0700 Subject: [PATCH 3/6] verilog: error out when non-ANSI task/func arguments --- frontends/verilog/verilog_parser.y | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index db9a130cf..b7c6af91e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -853,7 +853,11 @@ task_func_port: } if (astbuf2 && astbuf2->children.size() != 2) frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); - } wire_name | wire_name; + } wire_name | + { + if (!astbuf1) + frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + } wire_name; task_func_body: task_func_body behavioral_stmt | From 0d2c33f9f4f8ca1bb507e3e688e0c7d372f0247b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 10:11:45 -0700 Subject: [PATCH 4/6] tests: update/extend task argument tests --- tests/verilog/bug2042-sv.ys | 34 ++++++++++++++++++++++++++++++++++ tests/verilog/bug2042.ys | 3 +-- 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 tests/verilog/bug2042-sv.ys diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys new file mode 100644 index 000000000..9a0d419c8 --- /dev/null +++ b/tests/verilog/bug2042-sv.ys @@ -0,0 +1,34 @@ +read_verilog -sv < Date: Wed, 13 May 2020 13:33:37 -0700 Subject: [PATCH 5/6] verilog: default to input in sv mode if task/func has no dir ... otherwise error --- frontends/verilog/verilog_parser.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b7c6af91e..f250d7685 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -855,8 +855,16 @@ task_func_port: frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); } wire_name | { - if (!astbuf1) - frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + if (!astbuf1) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + albuf = new dict; + astbuf1 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + astbuf1->is_input = true; + astbuf2 = NULL; + } } wire_name; task_func_body: From 56a5b1d2daf1b244990d81f32183034071ebd185 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 08:36:36 -0700 Subject: [PATCH 6/6] test: add another testcase as per @nakengelhardt --- tests/verilog/bug2042-sv.ys | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys index 9a0d419c8..e815d7fc5 100644 --- a/tests/verilog/bug2042-sv.ys +++ b/tests/verilog/bug2042-sv.ys @@ -20,6 +20,31 @@ proc sat -verify -prove-asserts +design -reset +read_verilog -sv <