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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}

This commit is contained in:
Eddie Hung 2019-09-27 12:49:57 -07:00 committed by Marcin Kościelnicki
parent 4535f2c694
commit 5b5756b91e
6 changed files with 46 additions and 122 deletions
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44
techlibs/xilinx/cells_sim.v
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@ -384,6 +384,50 @@ module FDPE_1 (
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
module LDCE (
output reg Q,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
input D,
(* invertible_pin = "IS_G_INVERTED" *)
input G,
input GE
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
initial Q = INIT;
wire clr = CLR ^ IS_CLR_INVERTED;
wire g = G ^ IS_G_INVERTED;
always @*
if (clr) Q = 1'b0;
else if (GE && g) Q = D;
endmodule
module LDPE (
output reg Q,
input D,
(* invertible_pin = "IS_G_INVERTED" *)
input G,
input GE,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
initial Q = INIT;
wire g = G ^ IS_G_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
always @*
if (pre) Q = 1'b1;
else if (GE && g) Q = D;
endmodule
module RAM32X1D ( module RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=1153 *) (* abc_arrival=1153 *)

4
techlibs/xilinx/cells_xtra.py
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@ -108,8 +108,8 @@ XC6S_CELLS = [
# Cell('FDRE'), # Cell('FDRE'),
# Cell('FDSE'), # Cell('FDSE'),
Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
Cell('LDCE'), # Cell('LDCE'),
Cell('LDPE'), # Cell('LDPE'),
Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
# Slice/CLB primitives. # Slice/CLB primitives.

30
techlibs/xilinx/xc6s_cells_xtra.v
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@ -1793,36 +1793,6 @@ module IDDR2 (...);
input S; input S;
endmodule endmodule
module LDCE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
endmodule
module LDPE (...);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE;
endmodule
module ODDR2 (...); module ODDR2 (...);
parameter DDR_ALIGNMENT = "NONE"; parameter DDR_ALIGNMENT = "NONE";
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;

30
techlibs/xilinx/xc6v_cells_xtra.v
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@ -2648,36 +2648,6 @@ module IDDR_2CLK (...);
input S; input S;
endmodule endmodule
module LDCE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
endmodule
module LDPE (...);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE;
endmodule
module ODDR (...); module ODDR (...);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0; parameter INIT = 1'b0;

30
techlibs/xilinx/xc7_cells_xtra.v
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@ -5149,36 +5149,6 @@ module IDDR_2CLK (...);
input S; input S;
endmodule endmodule
module LDCE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
endmodule
module LDPE (...);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE;
endmodule
module ODDR (...); module ODDR (...);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0; parameter INIT = 1'b0;

30
techlibs/xilinx/xcu_cells_xtra.v
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@ -10731,36 +10731,6 @@ module IDDRE1 (...);
input R; input R;
endmodule endmodule
module LDCE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
endmodule
module LDPE (...);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
output Q;
input D;
(* invertible_pin = "IS_G_INVERTED" *)
input G;
input GE;
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE;
endmodule
module ODDRE1 (...); module ODDRE1 (...);
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0; parameter [0:0] IS_D1_INVERTED = 1'b0;