Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor

backends/blif/blif.cc

@@ -118,7 +118,7 @@ struct BlifDumper
 		for (auto &it : inputs) {
 			RTLIL::Wire *wire = it.second;
 			for (int i = 0; i < wire->width; i++)
-				fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
+				fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
 		}
 		fprintf(f, "\n");
 
@@ -126,7 +126,7 @@ struct BlifDumper
 		for (auto &it : outputs) {
 			RTLIL::Wire *wire = it.second;
 			for (int i = 0; i < wire->width; i++)
-				fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
+				fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
 		}
 		fprintf(f, "\n");
 

backends/edif/edif.cc

@@ -271,7 +271,7 @@ struct EdifBackend : public Backend {
 				} else {
 					fprintf(f, "          (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
 					for (int i = 0; i < wire->width; i++) {
-						RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
+						RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
 						net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
 					}
 				}

frontends/ilang/parser.y

@@ -369,13 +369,13 @@ sigspec:
 	TOK_ID '[' TOK_INT ']' {
 		if (current_module->wires.count($1) == 0)
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-		$$ = new RTLIL::SigSpec(current_module->wires[$1], 1, $3);
+		$$ = new RTLIL::SigSpec(current_module->wires[$1], $3);
 		free($1);
 	} |
 	TOK_ID '[' TOK_INT ':' TOK_INT ']' {
 		if (current_module->wires.count($1) == 0)
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-		$$ = new RTLIL::SigSpec(current_module->wires[$1], $3 - $5 + 1, $5);
+		$$ = new RTLIL::SigSpec(current_module->wires[$1], $5, $3 - $5 + 1);
 		free($1);
 	} |
 	'{' sigspec_list '}' {

kernel/rtlil.cc

@@ -1324,10 +1324,17 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
 	offset = 0;
 }
 
-RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
+RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
 {
 	this->wire = wire;
-	this->width = width >= 0 ? width : wire->width;
+	this->width = wire->width;
+	this->offset = 0;
+}
+
+RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
+{
+	this->wire = wire;
+	this->width = width;
 	this->offset = offset;
 }
 
@@ -1432,9 +1439,16 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
 	check();
 }
 
-RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
+RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
 {
-	chunks_.push_back(RTLIL::SigChunk(wire, width, offset));
+	chunks_.push_back(RTLIL::SigChunk(wire));
+	width_ = chunks_.back().width;
+	check();
+}
+
+RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
+{
+	chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
 	width_ = chunks_.back().width;
 	check();
 }
@@ -2134,7 +2148,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
 			std::vector<std::string> index_tokens;
 			sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
 			if (index_tokens.size() == 1)
-				sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str())));
+				sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
 			else {
 				int a = atoi(index_tokens.at(0).c_str());
 				int b = atoi(index_tokens.at(1).c_str());
@@ -2142,7 +2156,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
 					int tmp = a;
 					a = b, b = tmp;
 				}
-				sig.append(RTLIL::SigSpec(wire, b-a+1, a));
+				sig.append(RTLIL::SigSpec(wire, a, b-a+1));
 			}
 		} else
 			sig.append(wire);

kernel/rtlil.h

@@ -462,7 +462,8 @@ struct RTLIL::SigChunk {
 	int width, offset;
 	SigChunk();
 	SigChunk(const RTLIL::Const &value);
-	SigChunk(RTLIL::Wire *wire, int width, int offset);
+	SigChunk(RTLIL::Wire *wire);
+	SigChunk(RTLIL::Wire *wire, int offset, int width = 1);
 	SigChunk(const std::string &str);
 	SigChunk(int val, int width = 32);
 	SigChunk(RTLIL::State bit, int width = 1);
@@ -522,7 +523,8 @@ public:
 	SigSpec();
 	SigSpec(const RTLIL::Const &value);
 	SigSpec(const RTLIL::SigChunk &chunk);
-	SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0);
+	SigSpec(RTLIL::Wire *wire);
+	SigSpec(RTLIL::Wire *wire, int offset, int width = 1);
 	SigSpec(const std::string &str);
 	SigSpec(int val, int width = 32);
 	SigSpec(RTLIL::State bit, int width = 1);

kernel/sigtools.h

@@ -144,7 +144,7 @@ struct SigPool
 	{
 		RTLIL::SigSpec sig;
 		for (auto &bit : bits) {
-			sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
+			sig.append(RTLIL::SigSpec(bit.first, bit.second));
 			break;
 		}
 		return sig;
@@ -154,7 +154,7 @@ struct SigPool
 	{
 		RTLIL::SigSpec sig;
 		for (auto &bit : bits)
-			sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
+			sig.append(RTLIL::SigSpec(bit.first, bit.second));
 		sig.sort_and_unify();
 		return sig;
 	}

passes/abc/abc.cc

@@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 			clk_str = clk_str.substr(1);
 		}
 		if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
-			clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1));
+			clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0));
 	}
 
 	if (dff_mode && clk_sig.size() == 0)

passes/fsm/fsm_map.cc

@@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 	RTLIL::SigSpec cases_vector;
 
 	for (int in_state : fullstate_cache)
-		cases_vector.append(RTLIL::SigSpec(state_onehot, 1, in_state));
+		cases_vector.append(RTLIL::SigSpec(state_onehot, in_state));
 
 	for (auto &it : pattern_cache)
 	{
@@ -47,7 +47,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
 		for (int in_state : it.second)
 			if (fullstate_cache.count(in_state) == 0)
-				or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
+				or_sig.append(RTLIL::SigSpec(state_onehot, in_state));
 		or_sig.optimize();
 
 		if (or_sig.size() == 0)
@@ -215,7 +215,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 		for (size_t j = 0; j < state.bits.size(); j++)
 			if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
-				sig_a.append(RTLIL::SigSpec(state_wire, 1, j));
+				sig_a.append(RTLIL::SigSpec(state_wire, j));
 				sig_b.append(RTLIL::SigSpec(state.bits[j]));
 			}
 		sig_a.optimize();
@@ -223,7 +223,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 		if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
 		{
-			module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, 1, i), sig_a));
+			module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a));
 		}
 		else
 		{
@@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 			eq_cell->type = "$eq";
 			eq_cell->connections["\\A"] = sig_a;
 			eq_cell->connections["\\B"] = sig_b;
-			eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
+			eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i);
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				fullstate_cache.erase(tr.state_in);
 		}
 
-		implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, 1, i));
+		implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i));
 	}
 
 	if (encoding_is_onehot)
@@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				if (state.bits[j] == RTLIL::State::S1)
 					bit_idx = j;
 			if (bit_idx >= 0)
-				next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, 1, i));
+				next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
 		}
 		log_assert(!next_state_sig.has_marked_bits());
 		module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
@@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				sig_a = RTLIL::SigSpec(state);
 			} else {
 				sig_b.append(RTLIL::SigSpec(state));
-				sig_s.append(RTLIL::SigSpec(next_state_onehot, 1, i));
+				sig_s.append(RTLIL::SigSpec(next_state_onehot, i));
 			}
 		}
 

passes/memory/memory_share.cc

@@ -613,7 +613,7 @@ struct MemoryShareWorker
 					groups_en[key] = grouped_en->width;
 					grouped_en->width++;
 				}
-				en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key]));
+				en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
 			}
 
 			module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);

passes/opt/opt_clean.cc

@@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 	for (auto &it : module->wires) {
 		RTLIL::Wire *wire = it.second;
 		for (int i = 0; i < wire->width; i++) {
-			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
+			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1);
 			if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
 				assign_map.add(s1);
 		}

passes/proc/proc_mux.cc

@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 		if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
 		{
-			mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig));
+			mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
 		}
 		else
 		{
@@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 			eq_cell->connections["\\A"] = sig;
 			eq_cell->connections["\\B"] = comp;
-			eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++);
+			eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
 		}
 	}
 

passes/sat/eval.cc

@@ -260,8 +260,8 @@ struct VlogHammerReporter
 				for (int i = 0; i < int(inputs.size()); i++) {
 					RTLIL::Wire *wire = module->wires.at(inputs[i]);
 					for (int j = input_widths[i]-1; j >= 0; j--) {
-						ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
+						ce.set(RTLIL::SigSpec(wire, j), bits.back());
-						recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
+						recorded_set_vars.append(RTLIL::SigSpec(wire, j));
 						recorded_set_vals.bits.push_back(bits.back());
 						bits.pop_back();
 					}

passes/sat/miter.cc

@@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 					eqx_cell->parameters["\\Y_WIDTH"] = 1;
 					eqx_cell->parameters["\\A_SIGNED"] = 0;
 					eqx_cell->parameters["\\B_SIGNED"] = 0;
-					eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
+					eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
 					eqx_cell->connections["\\B"] = RTLIL::State::Sx;
 					eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
 					miter_module->add(eqx_cell);

passes/sat/share.cc

@@ -292,8 +292,8 @@ struct ShareWorker
 			supercell->connections["\\Y"] = y;
 			module->add(supercell);
 
-			RTLIL::SigSpec new_y1(y, y1.size());
+			RTLIL::SigSpec new_y1(y, 0, y1.size());
-			RTLIL::SigSpec new_y2(y, y2.size());
+			RTLIL::SigSpec new_y2(y, 0, y2.size());
 
 			module->connections.push_back(RTLIL::SigSig(y1, new_y1));
 			module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -405,8 +405,8 @@ struct ShareWorker
 			supercell->connections["\\Y"] = y;
 			supercell->check();
 
-			RTLIL::SigSpec new_y1(y, y1.size());
+			RTLIL::SigSpec new_y1(y, 0, y1.size());
-			RTLIL::SigSpec new_y2(y, y2.size());
+			RTLIL::SigSpec new_y2(y, 0, y2.size());
 
 			module->connections.push_back(RTLIL::SigSig(y1, new_y1));
 			module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -620,7 +620,7 @@ struct ShareWorker
 		RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
 		for (auto &p : activation_patterns) {
 			all_cases_wire->width++;
-			module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
+			module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1));
 		}
 		if (all_cases_wire->width == 1)
 			return all_cases_wire;

passes/techmap/extract.cc

@@ -315,7 +315,7 @@ namespace
 			RTLIL::Wire *wire = it.second;
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
-					sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i));
+					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
 				cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
 			}
 		}

passes/techmap/iopadmap.cc

@@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
 						RTLIL::Cell *cell = new RTLIL::Cell;
 						cell->name = NEW_ID;
 						cell->type = RTLIL::escape_id(celltype);
-						cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i);
+						cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
 						if (!portname2.empty())
-							cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i);
+							cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())