mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
The hierarchy pass does a lot more than just finding the top module, mainly resolving implicit (positional, wildcard) module connections. Fixes #2589.
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10c3214e56
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@ -2939,9 +2939,9 @@ struct CxxrtlWorker {
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}
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}
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void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init)
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void check_design(RTLIL::Design *design, bool &has_sync_init)
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{
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has_sync_init = has_top = false;
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has_sync_init = false;
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for (auto module : design->modules()) {
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if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
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@ -2953,9 +2953,6 @@ struct CxxrtlWorker {
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if (!design->selected_module(module))
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continue;
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if (module->get_bool_attribute(ID::top))
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has_top = true;
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for (auto proc : module->processes)
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for (auto sync : proc.second->syncs)
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if (sync->type == RTLIL::STi)
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@ -2966,10 +2963,10 @@ struct CxxrtlWorker {
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void prepare_design(RTLIL::Design *design)
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{
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bool did_anything = false;
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bool has_top, has_sync_init;
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bool has_sync_init;
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log_push();
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check_design(design, has_top, has_sync_init);
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if (run_hierarchy && !has_top) {
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check_design(design, has_sync_init);
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if (run_hierarchy) {
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Pass::call(design, "hierarchy -auto-top");
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did_anything = true;
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}
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@ -2990,7 +2987,7 @@ struct CxxrtlWorker {
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}
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// Recheck the design if it was modified.
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if (did_anything)
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check_design(design, has_top, has_sync_init);
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check_design(design, has_sync_init);
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log_assert(!has_sync_init);
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log_pop();
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if (did_anything)
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