riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Use ID()

This commit is contained in:
Eddie Hung 2019-08-16 16:38:49 -07:00
parent d26c512d7e
commit 5abe133323
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/techmap/abc9.cc
View File

@ -1086,16 +1086,16 @@ struct Abc9Pass : public Pass {
auto w = m->wire(p);
log_assert(w);
if (w->port_input) {
if (w->attributes.count("\\abc_scc_break"))
if (w->attributes.count(ID(abc_scc_break)))
scc_break_inputs[m->name].insert(p);
if (w->attributes.count("\\abc_carry_in")) {
if (w->attributes.count(ID(abc_carry_in))) {
if (carry_in)
log_error("Module '%s' contains more than one 'abc_carry_in' port.\n", log_id(m));
carry_in = w;
}
}
if (w->port_output) {
if (w->attributes.count("\\abc_carry_out")) {
if (w->attributes.count(ID(abc_carry_out))) {
if (carry_out)
log_error("Module '%s' contains more than one 'abc_carry_out' port.\n", log_id(m));
carry_out = w;