riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix minor typo in error message 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-10-25 13:20:00 +02:00
parent 6cd5b8b76b
commit 5ab58d4930
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/verilog/verilog_parser.y
View File

@ -1478,7 +1478,7 @@ behavioral_stmt:
node->str = *$3; node->str = *$3;
} behavioral_stmt_list TOK_END opt_label { } behavioral_stmt_list TOK_END opt_label {
if ($3 != NULL && $7 != NULL && *$3 != *$7) if ($3 != NULL && $7 != NULL && *$3 != *$7)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) doesn't match.", $3->c_str()+1, $7->c_str()+1); frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
if ($3 != NULL) if ($3 != NULL)
delete $3; delete $3;
if ($7 != NULL) if ($7 != NULL)