riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update tests with reduced area

This commit is contained in:
Eddie Hung 2020-01-21 16:50:04 -08:00
parent 72e4540ca9
commit 5aaa19f1ab
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tests/arch/ecp5/mux.ys
View File

@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-count 12 t:L6MUX21 select -assert-count 8 t:L6MUX21
select -assert-count 34 t:LUT4 select -assert-count 26 t:LUT4
select -assert-count 17 t:PFUMX select -assert-count 12 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

6
tests/arch/efinix/mux.ys
View File

@ -16,7 +16,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4 #select -assert-count 2 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D select -assert-none t:EFX_LUT4 %% t:* %D
@ -26,7 +26,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:EFX_LUT4 #select -assert-count 5 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D select -assert-none t:EFX_LUT4 %% t:* %D
@ -36,6 +36,6 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-count 12 t:EFX_LUT4 select -assert-count 11 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D select -assert-none t:EFX_LUT4 %% t:* %D