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Fix "scc" call inside abc9 to consider all wires

This commit is contained in:
Eddie Hung 2019-09-29 09:58:00 -07:00
parent f3e150d9a5
commit 5a4011e8c9
1 changed files with 1 additions and 1 deletions
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2
passes/techmap/abc9.cc
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@ -75,7 +75,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
void handle_loops(RTLIL::Design *design) void handle_loops(RTLIL::Design *design)
{ {
Pass::call(design, "scc -set_attr abc_scc_id {}"); Pass::call(design, "scc -set_attr abc_scc_id {} % w:*");
// For every unique SCC found, (arbitrarily) find the first // For every unique SCC found, (arbitrarily) find the first
// cell in the component, and select (and mark) all its output // cell in the component, and select (and mark) all its output