riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add unconditional match blocks for force RAM

This commit is contained in:
Eddie Hung 2019-12-16 13:31:15 -08:00
parent 6b384861e4
commit 5a00d5578c
2 changed files with 47 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
techlibs/xilinx/xc7_xcu_brams.txt
View File

@ -77,7 +77,25 @@ endbram
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
match $__XILINX_RAMB36_SDP
attribute !ram_style ram_style=block ram_block
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB36_SDP
attribute ram_style=block ram_block
attribute !logic_block
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB18_SDP
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
@ -87,7 +105,15 @@ match $__XILINX_RAMB36_SDP
endmatch
match $__XILINX_RAMB18_SDP
attribute !ram_style ram_style=block ram_block
attribute ram_style=block ram_block
attribute !logic_block
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB36_TDP
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
@ -97,7 +123,15 @@ match $__XILINX_RAMB18_SDP
endmatch
match $__XILINX_RAMB36_TDP
attribute !ram_style ram_style=block ram_block
attribute ram_style=block ram_block
attribute !logic_block
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
@ -107,10 +141,8 @@ match $__XILINX_RAMB36_TDP
endmatch
match $__XILINX_RAMB18_TDP
attribute !ram_style ram_style=block ram_block
attribute ram_style=block ram_block
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
endmatch

9
tests/arch/xilinx/blockram.ys
View File

@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
dump m:*
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1