mirror of https://github.com/YosysHQ/yosys.git
Martin Povišer
GitHub
commit
59a96470df
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@ -51,3 +51,4 @@ OBJS += passes/cmds/future.o
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OBJS += passes/cmds/box_derive.o
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OBJS += passes/cmds/example_dt.o
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OBJS += passes/cmds/portarcs.o
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OBJS += passes/cmds/wrapcell.o
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@ -0,0 +1,170 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "backends/rtlil/rtlil_backend.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters)
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{
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std::stringstream result;
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auto it = fmt.begin();
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while (it != fmt.end()) {
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if (*it == '{') {
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it++;
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auto beg = it;
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while (it != fmt.end() && *it != '}') it++;
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if (it == fmt.end()) {
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log("Unclosed curly brackets in format string '%s'\n", fmt.c_str());
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return {};
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}
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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} else {
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result << *it;
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}
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it++;
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}
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return {result.str()};
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}
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struct WrapcellPass : Pass {
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WrapcellPass() : Pass("wrapcell", "wrap individual cells into new modules") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" wrapcell -name <format> [selection]\n");
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log("\n");
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log("This command wraps the selected cells individually into modules. The name for\n");
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log("each wrapper module is derived from the template <format> by substituting\n");
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log("parameter values as specified in curly brackets. If the named module already\n");
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log("exists, it is reused.\n");
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log("\n");
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log(" -setattr <attribute-name>\n");
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log(" set the given boolean attribute on each created wrapper module\n");
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log("\n");
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log(" -formatattr <attribute-name> <format>\n");
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log(" set a string attribute on the created wrapper module by substituting\n");
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log(" parameter values into <format>\n");
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log("\n");
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log("Currently this command only supports wrapping internal cell types.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, Design *d) override
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{
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log_header(d, "Executing WRAPCELL pass. (wrap selected cells)\n");
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struct AttrRule {
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IdString name;
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std::string value_fmt;
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AttrRule(IdString name, std::string value_fmt)
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: name(name), value_fmt(value_fmt) {}
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};
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std::vector<AttrRule> attributes;
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std::string name_fmt;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-setattr" && argidx+1 < args.size()) {
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attributes.emplace_back(RTLIL::escape_id(args[++argidx]), "");
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} else if (args[argidx] == "-formatattr" && argidx+2 < args.size()) {
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IdString id = RTLIL::escape_id(args[++argidx]);
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attributes.emplace_back(id, args[++argidx]);
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} else if (args[argidx] == "-name" && argidx+1 < args.size()) {
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name_fmt = args[++argidx];
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} else {
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break;
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}
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}
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extra_args(args, argidx, d);
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if (name_fmt.empty())
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log_cmd_error("Argument -name required");
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CellTypes ct;
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ct.setup();
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for (auto module : d->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name)) {
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cell->type = name;
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cell->parameters.clear();
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continue;
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}
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if (!ct.cell_known(cell->type))
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log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
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log_id(cell->type), log_id(cell), log_id(module));
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Module *subm = d->addModule(name);
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Cell *subcell = subm->addCell("$1", cell->type);
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for (auto conn : cell->connections()) {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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if (ct.cell_output(cell->type, w->name))
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w->port_output = true;
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else
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w->port_input = true;
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subcell->setPort(conn.first, w);
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}
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subcell->parameters = cell->parameters;
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subm->fixup_ports();
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for (auto rule : attributes) {
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if (rule.value_fmt.empty()) {
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subm->set_bool_attribute(rule.name);
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} else {
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters);
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if (!value)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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subm->set_string_attribute(rule.name, value.value());
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}
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}
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cell->type = name;
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cell->parameters.clear();
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}
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}
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}
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} WrapcellPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,25 @@
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read_verilog <<EOF
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module top(
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input [1:0] a,
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input [2:0] b,
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output [2:0] y,
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input [2:0] a2,
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input [3:0] b2,
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output [3:0] y2,
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input [1:0] a3,
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input [2:0] b3,
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output [2:0] y3
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);
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assign y = a | (*keep*) b;
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assign y2 = a2 | (*keep*) b2;
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assign y3 = a3 | (*keep*) b3;
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endmodule
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EOF
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wreduce
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wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}
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select -assert-count 2 top/t:OR_2_3_3
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select -assert-count 1 top/t:OR_3_4_4
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select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
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select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
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select -assert-mod-count 2 A:bar=w3 A:bar=w4
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