riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add some spacing

This commit is contained in:
Eddie Hung 2019-07-10 12:32:33 -07:00
parent 521971e32e
commit 58bb84e5b2
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
techlibs/xilinx/cells_map.v
View File

@ -220,15 +220,15 @@ module \$__XILINX_SHIFTX (A, B, Y);
// This has the effect of more effectively utilising the hard mux; // This has the effect of more effectively utilising the hard mux;
// take for example a 5:1 multiplexer, currently this would map as: // take for example a 5:1 multiplexer, currently this would map as:
// //
// A[0] \___ __ A[0] \__ __ // A[0] \___ __ A[0] \__ __
// A[4] / \| \ whereas the more A[1] / \| \ // A[4] / \| \ whereas the more A[1] / \| \
// A[1] _____| | obvious mapping A[2] \___| | // A[1] _____| | obvious mapping A[2] \___| |
// A[2] _____| |-- of MSBs to hard A[3] / | |__ // A[2] _____| |-- of MSBs to hard A[3] / | |__
// A[3]______| | resources would A[4] ____| | // A[3]______| | resources would A[4] ____| |
// |__/ lead to: 1'bx ____| | // |__/ lead to: 1'bx ____| |
// || |__/ // || |__/
// || || // || ||
// B[1:0] B[1:2] // B[1:0] B[1:2]
// //
// Expectation would be that the 'forward' mapping (right) is more // Expectation would be that the 'forward' mapping (right) is more
// area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers