mirror of https://github.com/YosysHQ/yosys.git
opt_demorgan: skip zero width cells
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@ -39,6 +39,10 @@ void demorgan_worker(
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return;
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return;
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auto insig = sigmap(cell->getPort(ID::A));
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auto insig = sigmap(cell->getPort(ID::A));
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if (GetSize(insig) < 1)
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return;
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log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
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log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
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int num_inverted = 0;
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int num_inverted = 0;
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for(int i=0; i<GetSize(insig); i++)
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for(int i=0; i<GetSize(insig); i++)
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