mirror of https://github.com/YosysHQ/yosys.git
aiger: Support $anyinit cells
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021c3c8da5
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@ -189,6 +189,17 @@ struct AigerWriter
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continue;
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}
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if (cell->type == ID($anyinit))
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{
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auto sig_d = sigmap(cell->getPort(ID::D));
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auto sig_q = sigmap(cell->getPort(ID::Q));
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for (int i = 0; i < sig_d.size(); i++) {
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undriven_bits.erase(sig_q[i]);
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ff_map[sig_q[i]] = sig_d[i];
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}
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continue;
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}
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if (cell->type == ID($_AND_))
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{
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SigBit A = sigmap(cell->getPort(ID::A).as_bit());
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