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Added support for bit/part select to mem2reg rewriter

This commit is contained in:
Clifford Wolf 2014-07-17 13:49:32 +02:00
parent 6d69d4aaa8
commit 5867f6bcdc
2 changed files with 30 additions and 0 deletions
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9
frontends/ast/simplify.cc
View File

@ -1974,6 +1974,8 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
continue; continue;
AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK)); AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
AstNode *assign_reg = new AstNode(type, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER)); AstNode *assign_reg = new AstNode(type, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
if (children[0]->children.size() == 2)
assign_reg->children[0]->children.push_back(children[0]->children[1]->clone());
assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str.c_str(), i); assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str.c_str(), i);
assign_reg->children[1]->str = id_data; assign_reg->children[1]->str = id_data;
cond_node->children[1]->children.push_back(assign_reg); cond_node->children[1]->children.push_back(assign_reg);
@ -1990,6 +1992,10 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
if (type == AST_IDENTIFIER && id2ast && mem2reg_set.count(id2ast) > 0) if (type == AST_IDENTIFIER && id2ast && mem2reg_set.count(id2ast) > 0)
{ {
AstNode *bit_part_sel = NULL;
if (children.size() == 2)
bit_part_sel = children[1]->clone();
if (children[0]->children[0]->type == AST_CONSTANT) if (children[0]->children[0]->type == AST_CONSTANT)
{ {
int id = children[0]->children[0]->integer; int id = children[0]->children[0]->integer;
@ -2073,6 +2079,9 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
id2ast = NULL; id2ast = NULL;
str = id_data; str = id_data;
} }
if (bit_part_sel)
children.push_back(bit_part_sel);
} }
assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0); assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);

21
tests/simple/memory.v
View File

@ -134,3 +134,24 @@ always @(posedge clk) begin
end end
endmodule endmodule
// ----------------------------------------------------------
module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule