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Cleanups in xilinx bram descriptions

This commit is contained in:
Clifford Wolf 2015-01-07 01:28:18 +01:00
parent b26590f8ab
commit 584c5f3937
2 changed files with 36 additions and 36 deletions
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64
techlibs/xilinx/brams.v
View File

@ -209,8 +209,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.DIADI(16'b0), .DIADI(16'b0),
.DIPADIP(2'b0), .DIPADIP(2'b0),
.DOADO(DO[15:0]), .DOADO(DO),
.DOPADOP(DOP[1:0]), .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14), .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2), .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
.ENARDEN(|1), .ENARDEN(|1),
@ -219,8 +219,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.RSTREGARSTREG(|0), .RSTREGARSTREG(|0),
.WEA(2'b0), .WEA(2'b0),
.DIBDI(DI[15:0]), .DIBDI(DI),
.DIPBDIP(DIP[1:0]), .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14), .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3), .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1), .ENBWREN(|1),
@ -251,8 +251,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0}; wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0}; wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0};
wire DIP, DOP; wire [1:0] DIP, DOP;
wire [7:0] DI, DO; wire [15:0] DI, DO;
wire [8:0] A1DATA_BUF; wire [8:0] A1DATA_BUF;
reg [8:0] B1DATA_Q; reg [8:0] B1DATA_Q;
@ -268,8 +268,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF; assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
assign A1DATA_BUF = { DOP, DO }; assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP, DI } = B1DATA; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #( RAMB18E1 #(
.RAM_MODE("TDP"), .RAM_MODE("TDP"),
@ -282,7 +282,7 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.DIADI(16'b0), .DIADI(16'b0),
.DIPADIP(2'b0), .DIPADIP(2'b0),
.DOADO(DO[7:0]), .DOADO(DO),
.DOPADOP(DOP), .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14), .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2), .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@ -292,8 +292,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0), .RSTREGARSTREG(|0),
.WEA(2'b0), .WEA(2'b0),
.DIBDI({8'b0, DI}), .DIBDI(DI),
.DIPBDIP({1'b0, DIP}), .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14), .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3), .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1), .ENBWREN(|1),
@ -324,8 +324,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0}; wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0}; wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0};
wire DIP, DOP; wire [1:0] DIP, DOP;
wire [7:0] DI, DO; wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF; wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q; reg [3:0] B1DATA_Q;
@ -341,8 +341,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF; assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
assign A1DATA_BUF = { DOP, DO }; assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP, DI } = B1DATA; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #( RAMB18E1 #(
.RAM_MODE("TDP"), .RAM_MODE("TDP"),
@ -355,7 +355,7 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.DIADI(16'b0), .DIADI(16'b0),
.DIPADIP(2'b0), .DIPADIP(2'b0),
.DOADO(DO[7:0]), .DOADO(DO),
.DOPADOP(DOP), .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14), .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2), .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@ -365,8 +365,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0), .RSTREGARSTREG(|0),
.WEA(2'b0), .WEA(2'b0),
.DIBDI({8'b0, DI}), .DIBDI(DI),
.DIPBDIP({1'b0, DIP}), .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14), .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3), .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1), .ENBWREN(|1),
@ -397,8 +397,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0}; wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0}; wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0};
wire DIP, DOP; wire [1:0] DIP, DOP;
wire [7:0] DI, DO; wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF; wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q; reg [3:0] B1DATA_Q;
@ -414,8 +414,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF; assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
assign A1DATA_BUF = { DOP, DO }; assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP, DI } = B1DATA; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #( RAMB18E1 #(
.RAM_MODE("TDP"), .RAM_MODE("TDP"),
@ -428,7 +428,7 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.DIADI(16'b0), .DIADI(16'b0),
.DIPADIP(2'b0), .DIPADIP(2'b0),
.DOADO(DO[7:0]), .DOADO(DO),
.DOPADOP(DOP), .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14), .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2), .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@ -438,8 +438,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0), .RSTREGARSTREG(|0),
.WEA(2'b0), .WEA(2'b0),
.DIBDI({8'b0, DI}), .DIBDI(DI),
.DIPBDIP({1'b0, DIP}), .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14), .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3), .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1), .ENBWREN(|1),
@ -470,8 +470,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = A1ADDR; wire [13:0] A1ADDR_14 = A1ADDR;
wire [13:0] B1ADDR_14 = B1ADDR; wire [13:0] B1ADDR_14 = B1ADDR;
wire DIP, DOP; wire [1:0] DIP, DOP;
wire [7:0] DI, DO; wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF; wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q; reg [3:0] B1DATA_Q;
@ -487,8 +487,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF; assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
assign A1DATA_BUF = { DOP, DO }; assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP, DI } = B1DATA; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #( RAMB18E1 #(
.RAM_MODE("TDP"), .RAM_MODE("TDP"),
@ -501,7 +501,7 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.DIADI(16'b0), .DIADI(16'b0),
.DIPADIP(2'b0), .DIPADIP(2'b0),
.DOADO(DO[7:0]), .DOADO(DO),
.DOPADOP(DOP), .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14), .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2), .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@ -511,8 +511,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0), .RSTREGARSTREG(|0),
.WEA(2'b0), .WEA(2'b0),
.DIBDI({8'b0, DI}), .DIBDI(DI),
.DIPBDIP({1'b0, DIP}), .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14), .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3), .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1), .ENBWREN(|1),

8
techlibs/xilinx/tests/bram1_tb.v
View File

@ -83,16 +83,16 @@ module bram1_tb #(
xorshift64_next; xorshift64_next;
clk <= 0; clk <= 0;
for (i = 0; i < 256; i = i+1) begin for (i = 0; i < 512; i = i+1) begin
if (DBITS > 64) if (DBITS > 64)
WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state; WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
else else
WR_DATA <= xorshift64_state; WR_DATA <= xorshift64_state;
xorshift64_next; xorshift64_next;
WR_ADDR <= getaddr(i[7:4]); WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next; xorshift64_next;
RD_ADDR <= getaddr(i[3:0]); RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN <= ^i; WR_EN <= xorshift64_state[55];
xorshift64_next; xorshift64_next;
#1; clk <= 1; #1; clk <= 1;