mirror of https://github.com/YosysHQ/yosys.git
Small improvements in "abc" command handle_loops() function
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3aa003c8e9
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@ -287,8 +287,9 @@ static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edge
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log("Dumping loop state graph to slide %d.\n", ++nr);
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log("Dumping loop state graph to slide %d.\n", ++nr);
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fprintf(f, "digraph slide%d {\n", nr);
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fprintf(f, "digraph \"slide%d\" {\n", nr);
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fprintf(f, " rankdir=\"LR\";\n");
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fprintf(f, " label=\"slide%d\";\n", nr);
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fprintf(f, " rankdir=\"TD\";\n");
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std::set<int> nodes;
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std::set<int> nodes;
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for (auto &e : edges) {
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for (auto &e : edges) {
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@ -375,10 +376,10 @@ static void handle_loops()
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int id2 = edge_it.first;
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int id2 = edge_it.first;
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RTLIL::Wire *w1 = signal_list[id1].bit.wire;
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RTLIL::Wire *w1 = signal_list[id1].bit.wire;
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RTLIL::Wire *w2 = signal_list[id2].bit.wire;
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RTLIL::Wire *w2 = signal_list[id2].bit.wire;
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if (w1 != NULL)
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if (w1 == NULL)
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continue;
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else if (w2 == NULL)
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id1 = id2;
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id1 = id2;
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else if (w2 == NULL)
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continue;
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else if (w1->name[0] == '$' && w2->name[0] == '\\')
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else if (w1->name[0] == '$' && w2->name[0] == '\\')
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id1 = id2;
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id1 = id2;
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else if (w1->name[0] == '\\' && w2->name[0] == '$')
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else if (w1->name[0] == '\\' && w2->name[0] == '$')
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@ -387,7 +388,7 @@ static void handle_loops()
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id1 = id2;
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id1 = id2;
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else if (edges[id1].size() > edges[id2].size())
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else if (edges[id1].size() > edges[id2].size())
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continue;
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continue;
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else if (w2->name < w1->name)
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else if (w2->name.str() < w1->name.str())
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id1 = id2;
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id1 = id2;
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}
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}
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@ -396,6 +397,8 @@ static void handle_loops()
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continue;
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continue;
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}
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}
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log_assert(signal_list[id1].bit.wire != NULL);
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std::stringstream sstr;
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std::stringstream sstr;
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sstr << "$abcloop$" << (autoidx++);
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sstr << "$abcloop$" << (autoidx++);
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RTLIL::Wire *wire = module->addWire(sstr.str());
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RTLIL::Wire *wire = module->addWire(sstr.str());
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