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Add unsigned case

This commit is contained in:
Eddie Hung 2019-09-11 00:07:17 -07:00
parent 97e1520b13
commit 580faae8ad
1 changed files with 17 additions and 0 deletions
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17
tests/various/peepopt.ys
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@ -47,6 +47,23 @@ select -assert-count 0 t:*
#################### ####################
design -reset
read_verilog <<EOT
module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
always @(posedge clk) if (ce) o <= i;
endmodule
EOT
prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$dff r:WIDTH=2 %i
select -assert-count 1 t:$mux r:WIDTH=2 %i
select -assert-count 0 t:$dff t:$mux %% t:* %D
####################
design -reset design -reset
read_verilog <<EOT read_verilog <<EOT
module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);