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Cleaned up comments
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@ -194,19 +194,17 @@ namespace YOSYS_PYTHON {
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virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE
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{
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//log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
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//@TODO: Implement once necessary classes are wrapped
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}
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virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE
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{
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//log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
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//@TODO: Implement once necessary classes are wrapped
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}
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virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector<Yosys::RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
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{
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//log("#TRACE# New connections in module %s:\n", log_id(module));
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//for (auto &sigsig : sigsig_vec)
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// log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
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//@TODO: Implement once necessary classes are wrapped
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}
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virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE
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@ -214,10 +212,6 @@ namespace YOSYS_PYTHON {
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py_notify_blackout(new Module(module));
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}
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//virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { }
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//virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
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//virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
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virtual void py_notify_module_add(Module*){};
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virtual void py_notify_module_del(Module*){};
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virtual void py_notify_blackout(Module*){};
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