mirror of https://github.com/YosysHQ/yosys.git
cellhelp: Add default format parse for simcells
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst. Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
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@ -988,10 +988,14 @@ struct HelpPass : public Pass {
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}
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}
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else if (cell_help_messages.cell_help.count(args[1])) {
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else if (cell_help_messages.cell_help.count(args[1])) {
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SimHelper help_cell = cell_help_messages.cell_help.at(args[1]);
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SimHelper help_cell = cell_help_messages.cell_help.at(args[1]);
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if (help_cell.ver == "2") {
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if (help_cell.ver == "2" || help_cell.ver == "2a") {
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log("\n %s %s\n", help_cell.name.c_str(), help_cell.ports.c_str());
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log("\n %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str());
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log("\n%s\n", help_cell.title.c_str());
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if (help_cell.title != "") log("%s\n", help_cell.title.c_str());
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log("%s\n", help_cell.desc.c_str());
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std::stringstream ss;
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ss << help_cell.desc;
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for (std::string line; std::getline(ss, line, '\n');) {
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if (line != "::") log("%s\n", line.c_str());
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}
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log("Run 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
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log("Run 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
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log("\n");
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log("\n");
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} else {
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} else {
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@ -36,6 +36,24 @@ class SimHelper:
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val += f'cell_code[{json.dumps(self.name + "+")}] = tempCell;'
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val += f'cell_code[{json.dumps(self.name + "+")}] = tempCell;'
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return val
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return val
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def simcells_reparse(cell: SimHelper):
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# cut manual signature
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cell.desc = cell.desc[3:]
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# code-block truth table
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new_desc = []
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indent = ""
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for line in cell.desc:
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if line.startswith("Truth table:"):
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indent = " "
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new_desc.pop()
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new_desc.extend(["::", ""])
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new_desc.append(indent + line)
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cell.desc = new_desc
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# set version
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cell.ver = "2a"
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simHelper = SimHelper()
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simHelper = SimHelper()
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for line in fileinput.input():
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for line in fileinput.input():
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@ -62,7 +80,12 @@ for line in fileinput.input():
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# no module definition, ignore line
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# no module definition, ignore line
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pass
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pass
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if line.startswith("endmodule"):
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if line.startswith("endmodule"):
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short_filename = Path(fileinput.filename()).name
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if simHelper.ver == "1" and short_filename == "simcells.v":
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# default simcells parsing
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simcells_reparse(simHelper)
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if not simHelper.desc:
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if not simHelper.desc:
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# no help
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simHelper.desc.append("No help message for this cell type found.\n")
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simHelper.desc.append("No help message for this cell type found.\n")
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print(simHelper)
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print(simHelper)
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simHelper = SimHelper()
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simHelper = SimHelper()
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