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Support brams with initialization

This commit is contained in:
Miodrag Milanovic 2024-05-28 14:21:36 +02:00
parent 4aaab8f395
commit 5766555642
6 changed files with 267 additions and 222 deletions
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1
techlibs/nanoxplore/Makefile.inc
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@ -4,6 +4,7 @@ OBJS += techlibs/nanoxplore/nx_carry.o
# Techmap # Techmap
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))

16
techlibs/nanoxplore/brams.txt
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@ -2,38 +2,38 @@ ram block $__NX_RAM_ {
option "STD_MODE" "NOECC_48kx1" { option "STD_MODE" "NOECC_48kx1" {
# only 32k used # only 32k used
abits 15; abits 15;
widths 1 global; widths 1 per_port;
} }
option "STD_MODE" "NOECC_24kx2" { option "STD_MODE" "NOECC_24kx2" {
# only 16k used # only 16k used
abits 14; abits 14;
widths 2 global; widths 2 per_port;
} }
option "STD_MODE" "NOECC_16kx3" { option "STD_MODE" "NOECC_16kx3" {
abits 14; abits 14;
widths 3 global; widths 3 per_port;
} }
option "STD_MODE" "NOECC_12kx4" { option "STD_MODE" "NOECC_12kx4" {
# only 8k used # only 8k used
abits 13; abits 13;
widths 4 global; widths 4 per_port;
} }
option "STD_MODE" "NOECC_8kx6" { option "STD_MODE" "NOECC_8kx6" {
abits 13; abits 13;
widths 6 global; widths 6 per_port;
} }
option "STD_MODE" "NOECC_6kx8" { option "STD_MODE" "NOECC_6kx8" {
# only 4k used # only 4k used
abits 12; abits 12;
widths 8 global; widths 8 per_port;
} }
option "STD_MODE" "NOECC_4kx12" { option "STD_MODE" "NOECC_4kx12" {
abits 12; abits 12;
widths 12 global; widths 12 per_port;
} }
option "STD_MODE" "NOECC_2kx24" { option "STD_MODE" "NOECC_2kx24" {
abits 11; abits 11;
widths 24 global; widths 24 per_port;
} }
cost 64; cost 64;
init no_undef; init no_undef;

23
techlibs/nanoxplore/brams_init.vh Normal file
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@ -0,0 +1,23 @@
function [409600-1:0] bram_init_to_string;
input [49152-1:0] array;
input integer blocks;
input integer width;
reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
reg [24-1:0] temp2;
integer i;
integer j;
begin
temp = "";
for (i = 0; i < 2048; i = i + 1) begin
if (i != 0) begin
temp = {temp, ","};
end
temp2 = 24'b0;
for (j = 0; j < blocks; j = j + 1) begin
temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];
end
temp = {temp, $sformatf("%b",temp2[23:0])};
end
bram_init_to_string = temp;
end
endfunction

74
techlibs/nanoxplore/brams_map.v
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@ -1,18 +1,20 @@
module $__NX_RAM_ (...); module $__NX_RAM_ (...);
parameter INIT = 0; parameter INIT = 0;
parameter OPTION_STD_MODE = ""; parameter OPTION_STD_MODE = "NOECC_24kx2";
parameter PORT_A_WIDTH = 24;
parameter PORT_B_WIDTH = 24;
parameter WIDTH = 24;
parameter PORT_A_CLK_POL = 1; parameter PORT_A_CLK_POL = 1;
input PORT_A_CLK; input PORT_A_CLK;
input PORT_A_CLK_EN; input PORT_A_CLK_EN;
input PORT_A_WR_EN; input PORT_A_WR_EN;
input [15:0] PORT_A_ADDR; input [15:0] PORT_A_ADDR;
input [WIDTH-1:0] PORT_A_WR_DATA; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
wire [24-1:0] A_DATA; wire [24-1:0] A_DATA;
output [WIDTH-1:0] PORT_A_RD_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
parameter PORT_B_CLK_POL = 1; parameter PORT_B_CLK_POL = 1;
@ -20,49 +22,37 @@ input PORT_B_CLK;
input PORT_B_CLK_EN; input PORT_B_CLK_EN;
input PORT_B_WR_EN; input PORT_B_WR_EN;
input [15:0] PORT_B_ADDR; input [15:0] PORT_B_ADDR;
input [WIDTH-1:0] PORT_B_WR_DATA; input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
wire [24-1:0] B_DATA; wire [24-1:0] B_DATA;
output [WIDTH-1:0] PORT_B_RD_DATA; output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
generate `include "brams_init.vh"
if (OPTION_STD_MODE == "NOECC_48kx1") begin
assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}}; localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000:
assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}}; OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001:
end OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110:
else if (OPTION_STD_MODE == "NOECC_24kx2") begin OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010:
assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}}; OPTION_STD_MODE == "NOECC_8kx6" ? 16'b0000111111111111:
assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}}; OPTION_STD_MODE == "NOECC_6kx8" ? 16'b0000011011011011:
end OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
else if (OPTION_STD_MODE == "NOECC_16kx3") begin OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}}; 'bx;
assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
end localparam A_REPEAT = 24 / PORT_A_WIDTH;
else if (OPTION_STD_MODE == "NOECC_12kx4") begin localparam B_REPEAT = 24 / PORT_B_WIDTH;
assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}}; assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
end assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
else if (OPTION_STD_MODE == "NOECC_8kx6") begin
assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_6kx8") begin
assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_4kx12") begin
assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
end
else if (OPTION_STD_MODE == "NOECC_2kx24") begin
assign A_DATA = PORT_A_WR_DATA;
assign B_DATA = PORT_B_WR_DATA;
end
endgenerate
NX_RAM_WRAP #( NX_RAM_WRAP #(
.std_mode(OPTION_STD_MODE), .std_mode(OPTION_STD_MODE),
.mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1), .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
.mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1), .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
.pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
.pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
.raw_config0(4'b0000),
.raw_config1(raw_config1_val),
.mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.ACK(PORT_A_CLK), .ACK(PORT_A_CLK),
//.ACKS(PORT_A_CLK), //.ACKS(PORT_A_CLK),
@ -87,8 +77,8 @@ NX_RAM_WRAP #(
//.BERR(), //.BERR(),
.BCS(PORT_B_CLK_EN), .BCS(PORT_B_CLK_EN),
.BWE(PORT_B_WR_EN), .BWE(PORT_B_WR_EN),
.BA(B_DATA), .BA(PORT_B_ADDR),
.BI(PORT_B_WR_DATA), .BI(B_DATA),
.BO(PORT_B_RD_DATA) .BO(PORT_B_RD_DATA)
); );
endmodule endmodule

172
techlibs/nanoxplore/cells_bb.v
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@ -90,178 +90,6 @@ endmodule
// parameter ring = 0; // parameter ring = 0;
//endmodule //endmodule
(* blackbox *)
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
input AA1;
input AA10;
input AA11;
input AA12;
input AA13;
input AA14;
input AA15;
input AA16;
input AA2;
input AA3;
input AA4;
input AA5;
input AA6;
input AA7;
input AA8;
input AA9;
input ACK;
input ACKC;
input ACKD;
input ACKR;
output ACOR;
input ACS;
output AERR;
input AI1;
input AI10;
input AI11;
input AI12;
input AI13;
input AI14;
input AI15;
input AI16;
input AI17;
input AI18;
input AI19;
input AI2;
input AI20;
input AI21;
input AI22;
input AI23;
input AI24;
input AI3;
input AI4;
input AI5;
input AI6;
input AI7;
input AI8;
input AI9;
output AO1;
output AO10;
output AO11;
output AO12;
output AO13;
output AO14;
output AO15;
output AO16;
output AO17;
output AO18;
output AO19;
output AO2;
output AO20;
output AO21;
output AO22;
output AO23;
output AO24;
output AO3;
output AO4;
output AO5;
output AO6;
output AO7;
output AO8;
output AO9;
input AR;
input AWE;
input BA1;
input BA10;
input BA11;
input BA12;
input BA13;
input BA14;
input BA15;
input BA16;
input BA2;
input BA3;
input BA4;
input BA5;
input BA6;
input BA7;
input BA8;
input BA9;
input BCK;
input BCKC;
input BCKD;
input BCKR;
output BCOR;
input BCS;
output BERR;
input BI1;
input BI10;
input BI11;
input BI12;
input BI13;
input BI14;
input BI15;
input BI16;
input BI17;
input BI18;
input BI19;
input BI2;
input BI20;
input BI21;
input BI22;
input BI23;
input BI24;
input BI3;
input BI4;
input BI5;
input BI6;
input BI7;
input BI8;
input BI9;
output BO1;
output BO10;
output BO11;
output BO12;
output BO13;
output BO14;
output BO15;
output BO16;
output BO17;
output BO18;
output BO19;
output BO2;
output BO20;
output BO21;
output BO22;
output BO23;
output BO24;
output BO3;
output BO4;
output BO5;
output BO6;
output BO7;
output BO8;
output BO9;
input BR;
input BWE;
parameter mcka_edge = 1'b0;
parameter mckb_edge = 1'b0;
parameter mem_ctxt = "";
parameter pcka_edge = 1'b0;
parameter pckb_edge = 1'b0;
parameter pipe_ia = 1'b0;
parameter pipe_ib = 1'b0;
parameter pipe_oa = 1'b0;
parameter pipe_ob = 1'b0;
parameter raw_config0 = 4'b0000;
parameter raw_config1 = 16'b0000000000000000;
//parameter raw_l_enable = 1'b0;
//parameter raw_l_extend = 4'b0000;
//parameter raw_u_enable = 1'b0;
//parameter raw_u_extend = 8'b00000000;
parameter std_mode = "";
endmodule
// NX_RAM related // NX_RAM related
(* blackbox *) (* blackbox *)
module NX_ECC(CKD, CHK, COR, ERR); module NX_ECC(CKD, CHK, COR, ERR);

203
techlibs/nanoxplore/cells_sim.v
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@ -185,3 +185,206 @@ module NX_BFR(I, O);
assign O = data_inv ? ~I : I; assign O = data_inv ? ~I : I;
endmodule endmodule
(* abc9_box, lib_whitebox *)
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
input AA1;
input AA10;
input AA11;
input AA12;
input AA13;
input AA14;
input AA15;
input AA16;
input AA2;
input AA3;
input AA4;
input AA5;
input AA6;
input AA7;
input AA8;
input AA9;
input ACK;
input ACKC;
input ACKD;
input ACKR;
output ACOR;
input ACS;
output AERR;
input AI1;
input AI10;
input AI11;
input AI12;
input AI13;
input AI14;
input AI15;
input AI16;
input AI17;
input AI18;
input AI19;
input AI2;
input AI20;
input AI21;
input AI22;
input AI23;
input AI24;
input AI3;
input AI4;
input AI5;
input AI6;
input AI7;
input AI8;
input AI9;
output reg AO1;
output reg AO10;
output reg AO11;
output reg AO12;
output reg AO13;
output reg AO14;
output reg AO15;
output reg AO16;
output reg AO17;
output reg AO18;
output reg AO19;
output reg AO2;
output reg AO20;
output reg AO21;
output reg AO22;
output reg AO23;
output reg AO24;
output reg AO3;
output reg AO4;
output reg AO5;
output reg AO6;
output reg AO7;
output reg AO8;
output reg AO9;
input AR;
input AWE;
input BA1;
input BA10;
input BA11;
input BA12;
input BA13;
input BA14;
input BA15;
input BA16;
input BA2;
input BA3;
input BA4;
input BA5;
input BA6;
input BA7;
input BA8;
input BA9;
input BCK;
input BCKC;
input BCKD;
input BCKR;
output BCOR;
input BCS;
output BERR;
input BI1;
input BI10;
input BI11;
input BI12;
input BI13;
input BI14;
input BI15;
input BI16;
input BI17;
input BI18;
input BI19;
input BI2;
input BI20;
input BI21;
input BI22;
input BI23;
input BI24;
input BI3;
input BI4;
input BI5;
input BI6;
input BI7;
input BI8;
input BI9;
output reg BO1;
output reg BO10;
output reg BO11;
output reg BO12;
output reg BO13;
output reg BO14;
output reg BO15;
output reg BO16;
output reg BO17;
output reg BO18;
output reg BO19;
output reg BO2;
output reg BO20;
output reg BO21;
output reg BO22;
output reg BO23;
output reg BO24;
output reg BO3;
output reg BO4;
output reg BO5;
output reg BO6;
output reg BO7;
output reg BO8;
output reg BO9;
input BR;
input BWE;
parameter mcka_edge = 1'b0;
parameter mckb_edge = 1'b0;
parameter mem_ctxt = "";
parameter pcka_edge = 1'b0;
parameter pckb_edge = 1'b0;
parameter pipe_ia = 1'b0;
parameter pipe_ib = 1'b0;
parameter pipe_oa = 1'b0;
parameter pipe_ob = 1'b0;
parameter raw_config0 = 4'b0000;
parameter raw_config1 = 16'b0000000000000000;
//parameter raw_l_enable = 1'b0;
//parameter raw_l_extend = 4'b0000;
//parameter raw_u_enable = 1'b0;
//parameter raw_u_extend = 8'b00000000;
parameter std_mode = "";
reg [24-1:0] mem [2048-1:0]; // 48 Kbit of memory
/*integer i;
initial begin
for (i = 0; i < 2048; i = i + 1)
mem[i] = 24'b0;
end*/
wire [15:0] AA = { AA16, AA15, AA14, AA13, AA12, AA11, AA10, AA9, AA8, AA7, AA6, AA5, AA4, AA3, AA2, AA1 };
wire [23:0] AI = { AI24, AI23, AI22, AI21, AI20, AI19, AI18, AI17, AI16, AI15, AI14, AI13, AI12, AI11, AI10, AI9, AI8, AI7, AI6, AI5, AI4, AI3, AI2, AI1 };
wire [23:0] AO = { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 };
wire [15:0] BA = { BA16, BA15, BA14, BA13, BA12, BA11, BA10, BA9, BA8, BA7, BA6, BA5, BA4, BA3, BA2, BA1 };
wire [23:0] BI = { BI24, BI23, BI22, BI21, BI20, BI19, BI18, BI17, BI16, BI15, BI14, BI13, BI12, BI11, BI10, BI9, BI8, BI7, BI6, BI5, BI4, BI3, BI2, BI1 };
wire [23:0] BO = { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 };
always @(posedge ACK)
if (AWE)
mem[AA[10:0]] <= AI;
else
{ AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 } <= mem[AA[10:0]];
assign ACOR = 1'b0;
assign AERR = 1'b0;
always @(posedge BCK)
if (BWE)
mem[BA[10:0]] <= BI;
else
{ BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 } <= mem[BA[10:0]];
assign BCOR = 1'b0;
assign BERR = 1'b0;
endmodule