riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'map_cells_before_map_luts' into xc7srl

This commit is contained in:
Eddie Hung 2019-04-04 07:54:42 -07:00
parent 77755b5a66 d9cb787391
commit 572603409c
2 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/proc/proc_mux.cc
View File

@ -361,7 +361,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
} }
// Transform into a $shiftx where possible // Transform into a $shiftx where possible
if (shiftx && last_mux_cell->type == "$pmux") { if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux") {
// Create bit-blasted $shiftx-es that shifts by the address line used in the case statement // Create bit-blasted $shiftx-es that shifts by the address line used in the case statement
auto pmux_b_port = last_mux_cell->getPort("\\B"); auto pmux_b_port = last_mux_cell->getPort("\\B");
auto pmux_y_port = last_mux_cell->getPort("\\Y"); auto pmux_y_port = last_mux_cell->getPort("\\Y");

24
techlibs/xilinx/synth_xilinx.cc
View File

@ -118,17 +118,17 @@ struct SynthXilinxPass : public Pass
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
log(" opt -fast\n"); log(" opt -fast\n");
log("\n"); log("\n");
log(" map_luts:\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
log(" clean\n");
log("\n");
log(" map_cells:\n"); log(" map_cells:\n");
log(" techmap -map +/xilinx/cells_map.v\n"); log(" techmap -map +/xilinx/cells_map.v\n");
log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
log(" clean\n"); log(" clean\n");
log("\n"); log("\n");
log(" map_luts:\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
log(" clean\n");
log("\n");
log(" check:\n"); log(" check:\n");
log(" hierarchy -check\n"); log(" hierarchy -check\n");
log(" stat\n"); log(" stat\n");
@ -280,13 +280,6 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "opt -fast"); Pass::call(design, "opt -fast");
} }
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
Pass::call(design, "techmap -map +/xilinx/lut_map.v");
}
if (check_label(active, run_from, run_to, "map_cells")) if (check_label(active, run_from, run_to, "map_cells"))
{ {
Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "techmap -map +/xilinx/cells_map.v");
@ -295,6 +288,13 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "clean"); Pass::call(design, "clean");
} }
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
Pass::call(design, "techmap -map +/xilinx/lut_map.v");
}
if (check_label(active, run_from, run_to, "check")) if (check_label(active, run_from, run_to, "check"))
{ {
Pass::call(design, "hierarchy -check"); Pass::call(design, "hierarchy -check");