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Merge pull request #1886 from boqwxp/cleanup_connect 

Clean up `passes/cmds/connect.cc`.
This commit is contained in:
whitequark 2020-04-09 03:58:07 +00:00 committed by GitHub
parent 5f649fc19d 64a5936bd7
commit 570f43ec91
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 12 additions and 14 deletions
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26
passes/cmds/connect.cc
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@ -32,9 +32,9 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
for (auto &it : module->cells_) for (auto cell : module->cells())
for (auto &port : it.second->connections_) for (auto &port : cell->connections_)
if (ct.cell_output(it.second->type, port.first)) if (ct.cell_output(cell->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second); sigmap(port.second).replace(sig, dummy_wire, &port.second);
for (auto &conn : module->connections_) for (auto &conn : module->connections_)
@ -77,15 +77,13 @@ struct ConnectPass : public Pass {
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
RTLIL::Module *module = NULL; RTLIL::Module *module = nullptr;
for (auto &it : design->modules_) { for (auto mod : design->selected_modules()) {
if (!design->selected(it.second)) if (module != nullptr)
continue; log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
if (module != NULL) module = mod;
log_cmd_error("Multiple modules selected: %s, %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.first));
module = it.second;
} }
if (module == NULL) if (module == nullptr)
log_cmd_error("No modules selected.\n"); log_cmd_error("No modules selected.\n");
if (!module->processes.empty()) if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n"); log_cmd_error("Found processes in selected module.\n");
@ -130,7 +128,7 @@ struct ConnectPass : public Pass {
std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector(); std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector(); std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
for (size_t i = 0; i < lhs.size(); i++) for (size_t i = 0; i < lhs.size(); i++)
if (rhs[i].wire != NULL) if (rhs[i].wire != nullptr)
sigmap.add(lhs[i], rhs[i]); sigmap.add(lhs[i], rhs[i]);
} }
@ -172,14 +170,14 @@ struct ConnectPass : public Pass {
if (flag_nounset) if (flag_nounset)
log_cmd_error("Can't use -port together with -nounset.\n"); log_cmd_error("Can't use -port together with -nounset.\n");
if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0) if (module->cell(RTLIL::escape_id(port_cell)) == nullptr)
log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));
} }
else else
log_cmd_error("Expected -set, -unset, or -port.\n"); log_cmd_error("Expected -set, -unset, or -port.\n");