mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #755 from Icenowy/anlogic-dram-init
anlogic: implement DRAM initialization
This commit is contained in:
commit
56ca1e6afc
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@ -1,6 +1,7 @@
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OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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OBJS += techlibs/anlogic/anlogic_determine_init.o
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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@ -8,3 +9,4 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
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@ -0,0 +1,72 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AnlogicDetermineInitPass : public Pass {
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AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" anlogic_determine_init [selection]\n");
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log("\n");
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log("Determine the init value of cells that doesn't allow unknown init value.\n");
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log("\n");
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}
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Const determine_init(Const init)
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{
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for (int i = 0; i < GetSize(init); i++) {
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if (init[i] != State::S0 && init[i] != State::S1)
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init[i] = State::S0;
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}
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return init;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
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extra_args(args, args.size(), design);
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size_t cnt = 0;
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\EG_LOGIC_DRAM16X4")
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{
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cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
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cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
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cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
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cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
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cnt++;
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}
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}
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}
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log_header(design, "Updated %lu cells with determined init value.\n", cnt);
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}
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} AnlogicDetermineInitPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,16 @@
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.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
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INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
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INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
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INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
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.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
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INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
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INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
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INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
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.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
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INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
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INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
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INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
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.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
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INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
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INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
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INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
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@ -1,5 +1,5 @@
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bram $__ANLOGIC_DRAM16X4
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init 0
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init 1
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abits 4
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dbits 4
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groups 2
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@ -1,4 +1,5 @@
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module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter [63:0]INIT = 64'bx;
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input CLK1;
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input [3:0] A1ADDR;
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@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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input [3:0] B1DATA;
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input B1EN;
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EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
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EG_LOGIC_DRAM16X4 #(
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`include "dram_init_16x4.vh"
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) _TECHMAP_REPLACE_ (
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.di(B1DATA),
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.waddr(B1ADDR),
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.wclk(CLK1),
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@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
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{
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run("memory_bram -rules +/anlogic/drams.txt");
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run("techmap -map +/anlogic/drams_map.v");
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run("anlogic_determine_init");
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}
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if (check_label("fine"))
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