mirror of https://github.com/YosysHQ/yosys.git
Fixed two minor bugs in constant parsing
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parent
751fb33688
commit
56c7d1e266
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@ -182,7 +182,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
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if (str == endptr)
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if (str == endptr)
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len_in_bits = -1;
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len_in_bits = -1;
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// The "<bits>'s?[bodh]<digits>" syntax
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// The "<bits>'s?[bodhBODH]<digits>" syntax
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if (*endptr == '\'')
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if (*endptr == '\'')
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{
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{
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std::vector<RTLIL::State> data;
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std::vector<RTLIL::State> data;
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@ -194,15 +194,19 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
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switch (*(endptr+1))
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switch (*(endptr+1))
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{
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{
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case 'b':
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case 'b':
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case 'B':
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my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
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my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
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break;
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break;
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case 'o':
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case 'o':
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case 'O':
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my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
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my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
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break;
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break;
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case 'd':
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case 'd':
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case 'D':
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my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
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my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
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break;
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break;
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case 'h':
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case 'h':
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case 'H':
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my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
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my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
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break;
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break;
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default:
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default:
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@ -177,12 +177,12 @@ YOSYS_NAMESPACE_END
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"genvar" { return TOK_GENVAR; }
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"genvar" { return TOK_GENVAR; }
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"real" { return TOK_REAL; }
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"real" { return TOK_REAL; }
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[0-9]+ {
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[0-9][0-9_]* {
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frontend_verilog_yylval.string = new std::string(yytext);
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_CONST;
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return TOK_CONST;
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}
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}
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[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
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[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
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frontend_verilog_yylval.string = new std::string(yytext);
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_CONST;
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return TOK_CONST;
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}
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}
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